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atc260x datasheet latest version: 1.1 2012-06-10 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 2 1. declaration circuit diagrams and other information relating to products of actions semiconductor company, ltd. (?actions?) are included as a means of illustrating typical applications. consequently, complete information sufficient for construction is not necessarily given. although the information has been examined and is believed to be accurate, actions makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and disclaims any responsibility for inaccuracies. information in this document is provided solely to enable use of actions? products. the information presented in this document does not form part of any quotation or contract of sale. actions assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of actions? products, except as expressed in actions? terms and conditions of sale for. all sales of any actions products are conditional on your agreement of the terms and conditions of recently dated version of actions? terms and conditions of sale agreement dated before the date of your order. this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights, copyright, trademark rights, rights in trade secrets and/or know how, or any other intellectual property rights of actions or others, however denominated, whether by express or implied representation, by estoppel, or otherwise. information documented here relates solely to actions products described herein supersedes, as of the release date of this publication, all previously published data and specifications relating to such products provided by actions or by any other person purporting to distribute such information. actions reserve the right to make changes to specifications and product descriptions at any time without notice. contact your actions sales representative to obtain the latest specifications before placing your product order. actions product may contain design defects or errors known as anomalies or errata which may cause the products functions to deviate from published specifications. anomaly or ?errata? sheets relating to currently characterized anomalies or errata are available upon request. designers must not rely on the absence or characteristics of any features or instructions of actions? products marked ?reserved? or ?undefined.? actions reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. actions? products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. any and all such uses without prior written approval of an officer of actions and further testing and/or modification will be fully at the risk of the customer. copies of this document and/or other actions produc t literature, as well as the terms and conditions of sale agreement, may be obtained by visiting actions? website at http://www.actions-semi.com/ or from an authorized actions representative. th e word ?actions?, the actions? logo, whether used separately and/or in combination, and th e phase ?atc2279a? are trademarks of actions semiconductor company, ltd., names and brands of other companies and their products that may from time to time descriptively appear in this prod uct data sheet are the trademarks of their respective free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 3 holders; no affiliation, authorization, or endorsement by such persons is claimed or implied except as may be expressly stated therein. actions disclaims and excludes an y and all warranties, including without limitation any and all impl ied warranties of merchantability, fitness for a particular purpose, title, and against infringement and the like, and any and all warranties arisin g from any course of dealing or usage of trade. in no event shall actions be reliable for any direct, incidental, indirect, special, punitive, or consequential da mages; or for lost data, profits, savings or revenues of any kind; regardless of the form of action, whether based on contract; tort; negligence of actions or others; strict liability; breach of warranty; or otherwise; whether or not any remedy of buyer is held to have failed of its essential purpose, and whether actions has been advised of the possibility of such damages or not. additional support additional product and company information can be obtained by visiting the actions website at: http://www.actions-semi.com free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 4 2. contents 1. declarat ion.................................................................................................................... . 2 2. contents ....................................................................................................................... .. 4 3. revision history ............................................................................................................. 7 4. introduc tion................................................................................................................... . 8 4.1 over view................................................................................................................... ................... 8 4.2 feature .................................................................................................................... .................... 9 4.3 typical a pplications....................................................................................................... .......... 12 4.4 ordering information....................................................................................................... ........ 13 4.5 functions contrastive list ................................................................................................. ..... 13 5. absolute maxi mum ra ting ....................................................................................... 14 6. recommended operati ng conditions ..................................................................... 15 7. electronic char acteristics........................................................................................... 16 7.1 over shoot .................................................................................................................. ................ 16 7.2 electrostatic discharge (esd) .............................................................................................. .. 16 7.3 dc charac teristics......................................................................................................... ........... 16 8. control interface & register mapping ..................................................................... 18 8.1 control interface .......................................................................................................... ............ 18 8.2 register mapping........................................................................................................... .......... 19 9. clocking....................................................................................................................... 20 10. audio codec subsystem ......................................................................................... 21 10.1 features .................................................................................................................. ................ 21 10.2 audio diagram & signal path ............................................................................................. 22 10.3 audio electronic characteristics ......................................................................................... 23 10.4 register list ............................................................................................................. .............. 28 10.5 register description ...................................................................................................... ....... 29 11. power supply & manage ment subsystem .......................................................... 59 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 5 11.1 features.................................................................................................................. ................ 59 11.2 module description........................................................................................................ ....... 60 11.3 register list ............................................................................................................. .............. 70 11.4 register description ...................................................................................................... ....... 72 12. auxiliaty adc ......................................................................................................... 133 12.1 module description........................................................................................................ .... 133 12.2 register list ............................................................................................................. ........... 134 13. real-time clock .................................................................................................... 141 13.1 module description........................................................................................................ ..... 141 13.2 register list ............................................................................................................. ........... 143 14. infrared remote controller.................................................................................. 148 14.1 features .................................................................................................................. ............. 148 14.2features module description ............................................................................................ 148 14.3 register list ............................................................................................................. ........... 154 15. ethernet phy subsystem..................................................................................... 159 15.1features ................................................................................................................... ............. 159 15.2 function description...................................................................................................... .... 159 16. touch pannel......................................................................................................... 160 16.1 features .................................................................................................................. ............. 160 16.2 function description ...................................................................................................... .... 160 16.4 register list ............................................................................................................. ........... 162 16.5 register description ...................................................................................................... .... 162 17. interrupt controller ............................................................................................... 162 17.1 features.................................................................................................................. .............. 162 17.2 block diagram............................................................................................................. ........ 163 17.3 register list............................................................................................................. ............ 163 17.4 register description ...................................................................................................... ..... 164 18. general puppose i/o............................................................................................ 165 18.1 features.................................................................................................................. ............. 165 18.2 function description...................................................................................................... .... 165 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 6 18.3 registers list ............................................................................................................ .......... 165 18.4 register description ...................................................................................................... .... 166 19. pin descri ption...................................................................................................... 173 19.1 atc2605 pinassignment ................................................................................................... 173 19.2 ATC2603 pinassignment ................................................................................................... 174 19.3 atc2605/atc260 3 pin defi nition ................................................................................... 175 20 package and orde ring information......................................................................... 185 20.1 package drawing ........................................................................................................... .... 185 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 7 3. revision history date revision description 2012-01-10 1.0 new release 2012-06-10 1.1 add ATC2603 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 8 4. introduction 4.1 overview atc260x is an integrated audio and power management subsystem ic family, which provides a cost effective, single-chip solution for portable multimedia systems. and atc2605 with an ethernet phy build in. the integrated audio codec provides all the necessary functions for high-quality recording and playback, stereo or multi-channel (including 5.1 or 7.1). programmable on-chip amplifiers allow for the direct connection of headphones and microphones with a minimum of external components. a stereo class d or class ab dual mode amplifier is also build in. digita l microphone interface is supported. atc260x includes four programmable dc-dc converters, twelve low-dropout (ldo) regulators and two current limit switch to generate suitable supply voltages for each part of the system, on-chip phy and audio codec as well as off-chip components such as a digital core, memory chips, wifi and sensor modules. each of these is voltage progra mmable. the atc260x can be powered by a lithium battery, by a wall adaptor or usb. an on-chip battery charger supports both trickle charging and fast (constant current, constant voltage) charging of single-cell lithium batteries. the charge current, termination voltage, and charger time-out are programmable to suit diff erent types of batteries. internal power management circuitry controls the start-up and shutdown sequencing of supply voltages, as well as sleep and wake-up. it also detects and handles conditions such as over-voltage, over-current. the integrated ethernet phy is fully compliant with 100base-tx and 10base-t pmd level standards (ieee 802.3u, fddi-tp- pmd, and ieee 802.3) , with rmii and smii interface. this function is only included in atc2605. a 32.768khz crystal oscillator should be supplied to atc260x system to get an accuracy clock for real time clock (rtc) and an alarm function capable of waking up the system. the master clock can be input directly or generated by an crystal oscillator 24mhz or 25mhz. resistance touch panel, ir, multi-channel adc capable of waking up function is also integrated. all the information from the master soc is configured through spi interface. free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 9 4.2 feature audio codec z 7.1 channel dac, snr (a-weighting)>98db, thd<-80db. z two stereo adcs, snr(a-weighting)>91db, thd<-82db, for supporting multi channels dv microphone recording, difference or single-ended input both supported. z stereo 20mw pa (power amplifier) for headphone with 41 level volume control(volume update with zero-cross detection), traditional mode and direct drive mode, both with anti-pop circuit z dac supports sample rate 192k/96k/48k/32k/24k/16k/12k/8k/88.2k/44.1k/ 22.05k /11.025k. z adc supports sample rate 96k/48k/32k/24k/16k/12k/8k/44.1k/22.5k/11.025k z stereo digital microphone supported. z configurable high-pass filter with adc. z configurable agc/noise gate unit. z stereo, classd/classab dual mode amplifier, up to 2.5w when used as classd. z slave mode i2s, tdm mode only, tx and rx both. z 2.0/5.1/7.1 channel i2s receiver and 2.0/4 channel transmitter z i2s supports sample rate 192k/96k/48k/32k/24k/16k/12k/8k/88.2k/44.1k/ 22.05k/11.025k. power supply generation 4 dc-dc z dc-dc buck converter (0.7~1 .4v, up to 1200ma) (dc1) z dc-dc buck converter (1.3~2 .2v, up to 1000ma) (dc2) z dc-dc buck converter (2.6~3.3v, up to 1200 ma, when working without inductance in ldo mode, up to 800ma) (dc3) z dc-dc boost converter (3.0~5.5v, 8 00ma with external mosfet) (dc4) 12 ldo and 2 switch: z ldo voltage regulators (2.6~3.3v,400ma), high psrr (ldo1) z ldo voltage regulators (2.6~3.3v,200ma), high psrr (ldo2) z ldo voltage regulator (1.5-2.0v, 250ma) (ldo3) z ldo voltage regulators (2.8~3.5v,400ma), high psrr (ldo4) z ldo voltage regulators (2.6~3.3v,150ma), high psrr (ldo5) z ldo voltage regulator (0.7~1.4v, 200ma), high psrr (ldo6) z ldo voltage regulator (1.5-2.0v, 200ma), high psrr (ldo7) z ldo voltage regulators (2.3v - 3.3v, 150ma) , high psrr (ldo8) z ldo voltage regulator (1.0~1.5v, 150ma) , high psrr (ldo9) z ldo voltage regulator (2.3~3.3v, 100ma) , high psrr (ldo10) free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 10 z ldo voltage regulator (1.5~2.0v, 5ma), for rtc use (ldo11) z ldo voltage regulator (2.6~3.3v, 15ma), for standby use (ldo12) z two switch, configurable to ldo mode z over-voltage, over-current, over-temperature protection of dc-dcs and ldos battery charger z single-cell li-battery charger z thermal protection for charge control; z a backup battery charger power saving mode z several power saving mode including standby mode, sleep mode and deep-sleep mode. z ?always on? rtc with wake-up alarm z in deep-sleep with rtc always on, the cu rrent of ibat can be less than 20ua ethernet phy z rmii interface support with 50mhz reference clock output to mac z smii interface support with 125mhz reference clock output to mac z single-chip 10base-t and 100bas e-tx physical layer solution z fully compliant to 100base-tx/10base-t stan dards (ieee 802.3u, fdd i-tp-pmd, and ieee 802.3) z supports two multi-functional led output z supports the full-duplex and half-duplex modes z supports auto-mdix for detection and correction with the mdi/mdix auto -crossover function system control z spi slave interface z handles power sequencing, power-on reset signal, sleep mode signal and fault conditions interrupt signal z adaptive power distribute system, autonomous power source selection (battery, wall adaptor or usb bus) additional features z resistance touch panel with 12-bit resolution adc, can be used as wake-up source z a multi-channel 10-bit adc, can be used as voltage, current measurement or wake-up sources as romote control. z an extirq to master soc z a few configurable gpio pins z 24mhz or 25mhz system clock input supported z esd level of hbm can reach 4000v of all ios z atc2605, eplqfp128 package, 14*14mm, with 0.4mm pin pitch free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 11 z ATC2603, qfn68 package, 8*8mm, with 0.4mm pin pitch free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 12 ? 4.3 typical applications free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 13 4.4 ordering information part numbers package size atc2605 eplqfp128 14*14mm ATC2603 qfn68 8*8mm 4.5 functions contrastive list features atc2605 ATC2603 package eplqfp128 qfn68 dcdc 4 3 ldo 12 9 switch 2 1 codec class d 2 1 mic 2 1 hp out fmin 7.1 chanel x charger ethernet phy x control interface 4wire spi 4wire spi i2s 6wire 4wire resistence tp x remote adc general adc 4 2 rtc ir free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 14 5. absolute maximum rating these absolute maximum ratings are stress ratings, operating at or beyond these ratings can result in permanent damage. unless otherwise designated all voltages are relative to ground. parameter symbol min max unit ambient temperature tamb -30 +70 storage temperature tstg -55 +150 supply voltage dcxin/wall/vbus/bat/syspwr -0.3 6 v digital io -0.3 3.6 v input voltage analog io -0.3 3.6 v free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 15 6. recommended operating conditions parameter symbol min typ max unit wall adapter input source wall 4 5.5 v usb vbus input source vbus 4.75 5.25 v battery input source bat 3 4.2 v supply voltage dc x vin /ldo x in/sw x in 3 5.5 v class d supply voltage cdpvcc x 0 5.5 v core supply vdd 1.2 v io supply vcc 3.1 v ground gnd/agnd/dc x gnd/cdpgnd x 0 v free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 16 7. electronic characteristics 7.1 overshoot the maximum dc voltage on supply power pins is below 6v. however, during voltage transitions, the device can tolerate overshoot for up to 10us, as shown in figure below parameter symbol start max unit supply voltage dcxin/wall/vbus/ bat -0.3 8 v exposure to overshoot conditions for too many times may affect device reliability. atc260x can tolerate 1,000 times of such pulses 7.2 electrostatic discharge (esd) parameter pin unit human body model (hbm) all 4 kv 7.3 dc characteristics 3.1v i/os, free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 17 vcc = 3.1v, ta = 0 to 70 c parameter symbol min. typ. max. unit low-level input voltage v il 0.8 v high-level input voltage v ih 2.0 v low-level output voltage v ol 0.4 v high-level output voltage v oh 2.4 v 2.5v i/o s, vddr = 2.5v, ta = 0 to 70 c parameter symbol min. typ. max. unit low-level output voltage v ol 0.4 v high-level output voltage v oh 2.0 v free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 18 8. control interface & register mapping 8.1 control interface all functions in atc260x should be accessed thou ght a standard spi interface, configure into the registers or get information. it supported spi slave mode 3 only, and the bit rate is up to 10 mbps. there are 15 bits transmitted for address with 12bits register address and 3bits reserved (do not care), 16 bits for data, and 1 bit indicate the w/r signal of the register need be accessed. figure 0-1 spi write timing figure 0-2 spi read timing free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 19 8.2 register mapping 15 bits transmitted for address of the register need be accessed. the address mapping of these registers is described as follow: start end size(12bit) function module pmu aux adc rtc 0x 0 000 0x0ff 0x100 irc 0x 0 100 0x1ff 0x100 cmu 0x 0 200 0x2ff 0x100 ints 0x 0 300 0x3ff 0x100 mfp 0x 0 400 0x4ff 0x100 audio 0x 0 500 0x5ff 0x100 ethernet phy 0x 0 600 0x6ff 0x100 tp controller 0x0700 0xfff 0x900 reserved free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 20 9. clocking a 32.768khz crystal oscillator should be supplied to atc260x system to get an accuracy clock for real time clock (rtc) and an alarm function capable of waking up the system. if the clock requirement is not so accurate, an internel oscillator is build in for self use figure losc block diagram (rtcvdd) the master clock of atc260x operation can be input directly by the cpu clock output or generated by an external crystal oscillator, 24mhz or 25mhz. figure hosc block diagram (avcc) hosci hosco hosc (24/25mhz) ` c2 c1 300kohm 24/25mhz hosc_bonding=1 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 21 10. audio codec subsystem 10.1 features z the audio codec subusystem include i2s interface, dac, adc, and classd/classab ap. z slave mode i2s, tdm mode only, tx and rx both. z 2.0/5.1/7.1 channel i2s receiver and 2.0/4 channel transmitter z i2s supports sample rate 192k/96k/48k/32k/24k/16k/12k/8k/88.2k/44.1k/ 22.05k/11.025k. z 7.1 channel dac, snr (a-weighting)>98db, thd<-80db. dac supports sample rate 192k/96k/48k/32k/24k/16k/12k/8k/88.2k/44.1k/ 22.05k /11.025k. z stereo 20mw pa (power amplifier) for headphone with 41 level volume control(volume update with zero-cross detection), traditional mode and direct drive mode, both with anti-pop circuit z two stereo adcs, snr (a-weighting)>91db, thd<-82db, for supporting multi channels dv microphone recording, difference or single-ended input both supported. z adc supports sample rate 96k/48k/32k/24k/16k/12k/8k/44.1k/22.5k/11.025k z stereo digital microphone supported. z configurable high-pass filter with adc. z configurable agc/noise gate unit. z stereo, classd/classab dual mode amplifier, up to 2.5w when used as classd. free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 22 10.2 audio diagram & signal path + m u x - modulator - dac stereo adc0_en l+r dac_en l+r_mute mic0_en fm_en dac_l+r_analog_en mic_mix_en fm_mix_en pa_volue adc0_mux_sel mic0_gain fm_gain adc0_gain da_a sw+c dac_en sl+sr dac_en sbl+sbr dac_en dac_sw+c_analog_en pa_volue da_a dac_sl+sr_analog_en pa_volue da_a dac_sbl+sbr_analog_en pa_volue da_a headset outsw /outc outsl /outsr outsbl /outsbr fminl /fminr high pass filter digital audio if lrclk1 i2sdout lrclk0 i2sdin adc0_gain hpf bypass sw+c_mute sl+sr_mute sbl+sbr_mute stereo speaker outfl /outfr dmic decimation stereo dmic_dat dmic_clk mclk0 mclk1 mic1in l /mic1inr mic1_en mic1_gain - modulator stereo adc1_en high pass filter adc1_gain hpf bypass adc1_gain - dac - dac - dac power amplifier fl sw c sl sr sbl sbr fr mic0in l /mic0inr out1p/n out0p/n cld/clab amplifier free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 23 10.3 audio electronic characteristics test condition: avcc=2.9v, vcc=3.1v, vdd=avdd=vref= 1.5v, cdpvcc=5v. when testing dac+pa or pa a 16 or 32 ohm load should be included and when testing classd/classab a 4 ohm load should be included. 10.3.1 dac+pa dac + direct drive pa characteristics min typ max unit noise 9.6 uv snr 94 db snr(a-weighting) 97.8 db dynamic range (-48db input) 92.7 db dynamic range (a-weighting, -48db input) 96 db thd+n (0db input) -80 db max ampl (0db input) 576 mv max power 20.2 mw interchannel isolation (1k,0db input) -80/-81 (lmute/rmute) db dac + non direct drive pa characteristics min typ max unit noise 10 uv snr 95 db snr(a-weighting) 97.4 db dynamic range (-48db input) 93.6 db dynamic range (a-weighting, -48db input) 96.5 db thd+n (0db input) -82 db max ampl (0db input) 563 mv max power 19.22@220uf mw interchannel isolation (1k,0db input) -78/-78 (lmute/rmute) db free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 24 frequency response: dac+pa? 0 100 200 300 400 500 600 40 80 200 400 1000 2000 1000 0 1400 0 2000 0 ?(hz) (mv) fft: free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 25 10.3.2 pa non direct drive pa characteristics min typ max unit noise 11.2 uv snr 95 db dynamic range 93.7 db total harmonic distortion+noise -85 db output common mode voltage 1.506 vrms full scale output voltage@-60db thd+n 0.638vrms (1.958vpp input) vrms output power @16.5ohm 25.3 mw frequency response: thd+n vs input amp curve free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 26 direct drive pa characteristics min typ max unit noise 12 uv snr 94.4 db dynamic range 93 db total harmonic distortion+noise -84 db output common mode voltage 1.506/1.506/1.510 al/ar/vro vrms full scale output voltage@-60db thd+n 0.636vrms (@1.913vpp) vrms output power @16ohm 25.3 mw frequency response: free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 27 thd+n vs input amp curve free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 28 10.3.3 adc dynamic range (?40 dbfs input) 89.6@48k db total harmonic distortion+noise 85.5@48k db 10.3.4 classd/classab classd@5v: characteristics min tpy cld1/cld2 max unit snr 83.3 db snr(a-weighting) 86.3 db thd+n (1w) -72 db max power (-20db thd) 2.3 w max power (-40db thd) 1.87 w effectioncy (2.3w) 78 % classdab@5v characteristics min typ clab1/clab2 max unit snr 81 db snr(a-weighting) 83.5 db thd+n (500mw) -70/-70 db max power (-20db thd) 0.98 w max power (-40db thd) 0.74 w effectioncy (max w) 44.8% % 10.4 register list table 0-1 audio out controller registers address n ame base address a udio_in_out_registe r 0x0400 table dac/pa/iis/classd registers free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 29 offset register name description 0x00 audioinout_ctl audio in/out control for i2s register 0x02 dac_filterctl0 dac control for dac filter sample rate register 0x03 dac_filterctl1 dac control for digital filter bandwidth register 0x04 dac_digitalctl dac control en&mute register 0x05 dac_volumectl0 dac fl&fr volume control register 0x06 dac_volumectl1 dac sw&c volume control register 0x07 dac_volumectl2 dac sl&sr volume control register 0x08 dac_volumectl3 dac sbl&sbr volume control register 0x09 dac_analog0 dac analog 0 register 0x0a dac_analog1 dac analog 1 register 0x0e classd_ctl0 class d control 0 register 0x0f classd_ctl1 class d control 1 register 0x10 classd_ctl2 class d control 2 register 0x11 adc0_digitalctl adc0 digital control register 0x12 adc0_hpfctl adc0 high pass filter control register 0x13 adc0_ctl adc0 control register 0x14 agc0_ctl0 agc0 control 0 register 0x15 agc0_ctl1 agc0 control 1 register 0x16 agc0_ctl2 agc0 control 2 register 0x17 adc_analog0 adc analog 0 register 0x18 adc_analog1 adc analog 1 register 0x19 adc1_digitalctl adc1 digital control register 0x1a adc1_ctl adc1 control register 0x1b agc1_ctl0 agc1 control 0 register 0x1c agc1_ctl1 agc1 control 1 register 0x1d agc1_ctl2 agc1 control 2 register 10.5 register description audioinout_ctl audio in/out control for i2s register offset = 0x00 bit(s) name description r/w reset 15 reserved rw 0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 30 13 12 eidr earphone input detect irq 0: disable 1: enable rw 0 11 mdd mclk divided to dac 0:div=1 1:div=2 rw 0 10 ohscien class d overheat or short circuit warning irq enable 0: disable 1: enable this bit when enable will enable an interrupt signal to the interrupt controller, while classd_ctl0 bit 5 and bit 6 are enable and classd_ctl2 bit 12 15 is pulled high. rw 0 9 ocien direct drive output over current status irq 1: enable 0: disable this bit when enable will enable an interrupt signal to the interrupt controller, while dac_analog2 bit5 enable and dac_analog3 bit8 pulls high. rw 0 8 oen i2s output enable. 0: disable 1: enable rw 0 7 omd i2s_output mode: 0: 2.0-channel mode 1: 4-channel tdm mode a note in 2.0 -channel mode, when adc0 is enable, the output 2 channel of i2s tx is adc0 l and r channel. when adc1 is enable, the output 2 channel of i2s tx is adc1 l and r channel. in 4.0 -channel mode, adc0 and adc1 all must be enable, the output 4 channel of i2s tx is adc0l, adc0r, adc1l, adc1r. rw 0 6:5 ims i2s rx&tx mode select 00 3 wires mode 01 4 wires mode 10 6 wires mode 11 reserved rw 00 4 lb i2s loop back enable: 0: disable 1: enable rw 0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 31 3:2 imd i2s_input mode: 00: 2.0-channel mode 01: 5.1-channel tdm mode a 10: 7.1-channel tdm mode a 11 reserved rw 00 1 inen i2s input enable. 0: disable 1: enable rw 0 0 reserved rw 0 dac_filterctl0 dac control for dac filter sample rate register offset = 0x02 bit(s) name description r/w reset 15:13 - reserved r 0 12 dedsbl&sbr dacsbl&sbr en_dith 1:enable 0:disable rw 0 11 dedsl&sr dacsl&sr en_dith 1:enable 0:disable rw 0 10 dedsw&c dacsw&c en_dith 1:enable 0:disable rw 0 9 dedfl&fr dacfl&fr en_dith 1:enable 0:disable rw 0 8 disrs dac input sample rate sel 0:mclk/256 1:mclk/128 rw 0 7:6 dosrssbl&sbr dac sbl&sbr output sample rate sel 00:mclk/16 01:mclk/8 10:mclk/4 11:mclk/2 rw 00 5:4 dosrssl&sr dac sl&sr output sample rate sel 00:mclk/16 rw 00 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 32 01:mclk/8 10:mclk/4 11:mclk/2 3:2 dosrssw&c dac sw&c output sample rate sel 00:mclk/16 01:mclk/8 10:mclk/4 11:mclk/2 rw 00 1:0 dosrsfl&fr dac fl&fr output sample rate sel 00:mclk/16 01:mclk/8 10:mclk/4 11:mclk/2 rw 00 note: in da_d test mode, dac output sample rate should not be set to ?11? (mclk/2). dac_ filterctl1 dac control for digital filter bandwidth register offset = 0x03 bit(s) name description r/w reset 15 8 reserved r 0 7 6 dbwsbl&sbr dacsbl&sbr bandwidth 00:wide 01:middle 10:narrow 11:reserved rw 00 5 4 dbwsl&sr dacsl&sr bandwidth 00:wide 01:middle 10:narrow 11:reserved rw 00 3 2 dbwsw&c dacsw&c bandwidth 00:wide 01:middle 10:narrow 11:reserved rw 00 1 0 dbwfl&fr dacfl&fr bandwidth rw 00 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 33 00:wide 01:middle 10:narrow 11:reserved dac_digitalctl dac control en&mute register offset = 0x04 bit(s) name description r/w reset 15 dmsbr dacsbr digital mute 1:mute 0:not mute rw 0 14 dmsbl dacsbl digital mute 1:mute 0:not mute rw 0 13 dmsr dacsr digital mute 1:mute 0:not mute rw 0 12 dmsl dacsl digital mute 1:mute 0:not mute rw 0 11 dmc dacc digital mute 1:mute 0:not mute rw 0 10 dmsw dacsw digital mute 1:mute 0:not mute rw 0 9 dmfr dacfr digital mute 1:mute 0:not mute rw 0 8 dmfl dacfl digital mute 1:mute 0:not mute rw 0 7 desbr dacsbr digital enable 1:enable 0:disable rw 0 6 desbl dacsbl digital enable rw 0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 34 1:enable 0:disable 5 desr dacsr digital enable 1:enable 0:disable rw 0 4 desl dacsl digital enable 1:enable 0:disable rw 0 3 dec dacc digital enable 1:enable 0:disable rw 0 2 desw dacsw digital enable 1:enable 0:disable rw 0 1 defr dacfr digital enable 1:enable 0:disable rw 0 0 defl dacfl digital enable 1:enable 0:disable rw 0 dac_ volumectl0 dac fl&fr volume control (3/8 db/level) offset = 0x5 bit(s) name description r/w reset 15:8 dacfr_volume volume control 3/8 db/level ffh +24 db ?? bfh : 0 db beh : -3/8 db ?? 00h : -72 db rw be free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 35 7:0 dacfl_volume volume control 3/8 db/level ffh +24 db ?? bfh : 0 db beh : -3/8 db ?? 00h : -72 db rw be dac_ volumectl1 dac sw&c volume control (3/8 db/level) offset = 0x6 bit(s) name description r/w reset 15:8 dacc_volme volume control 3/8 db/level ffh +24 db ?? bfh : 0 db beh : -3/8 db ?? 00h : -72 db rw be 7:0 dacsw_volume volume control 3/8 db/level ffh +24 db ?? bfh : 0 db beh : -3/8 db ?? 00h : -72 db rw be dac_ volumectl2 dac sl&sr volume control 3/8 db/level offset = 0x7 bit(s) name description r/w reset free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 36 15:8 dacsr_volme dac6_volme control 3/8 db/level ffh +24 db ?? bfh : 0 db beh : -3/8 db ?? 00h : -72 db rw be 7:0 dacsl_volme dac5_volme control 3/8 db/level ffh +24 db ?? bfh : 0 db beh : -3/8 db ?? 00h : -72 db rw be dac_ volumectl3 dac sbl&sbr volume control 3/8 db/level offset = 0x8 bit(s) name description r/w reset 15:8 dacsbr_volme dac8_volme control 3/8 db/level ffh +24 db ?? bfh : 0 db beh : -3/8 db ?? 00h : -72 db rw be 7:0 dacsbl_volme dac7_volme control 3/8 db/level ffh +24 db ?? bfh : 0 db beh : -3/8 db ?? 00h : -72 db rw be free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 37 dac_analog0 dac analog register offset = 0x9 bit(s) name description r/w reset 15:4 -- reserved r 010100110101 3 kfen karaoke mix function enable 0 disable 1 enable note when enable this bit, mic0inl and mic0inr will be added and transmitted to pa rw 0 2:0 -- reserved r 101 dac_analog1 dac analog register offset = 0xa bit(s) name description r/w reset 15 micmute mic mute, 0: mute 1: not mute rw 0 14 fmmute fm mute, 0: mute 1: not mute rw 0 13 dacsbl&sbrmute dacsbl&sbr playback mute 0: mute dac playback, 1: enable dac playback rw 0 12 dacsl&srmute dacsl&sr playback mute 0: mute dac playback, 1: enable dac playback rw 0 11 dacsw&cmute dacsw&c playback mute 0: mute dac playback, 1: enable dac playback rw 0 10 dacfl&frmute dacfl&fr playback mute 0: mute dac playback, rw 0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 38 1: enable dac playback 9:6 -- reserved r 000 5:0 volume headphone amp volume control. total 41 level (values between 000000b and 101000b are valid. any value over 101000b set to it will be taken as 101000b actually. reading value will just show what you have written to it.) rw 000000 classd_ctl0 class d control 0 register offset = 0xe bit(s) name description r/w reset 15:13 otpr over temperature protect range 000: 103 / 65 deg 001: 114 / 72 deg 010: 125 / 77 deg 011: 138 / 84 deg 100: 147 / 89 deg 101: 158 / 94 deg 110: 170 / 99 deg 111: 190 / 104 deg rw 100 12:11 gain gain select 00: 12db 01: 18db 10: 24db 11: 30db rw 00 10 dbgin debug mode , input h or l to power stage 1: input h, power stage output l 0: input l ,power stage output h rw 0 9 nclpen non-clip enable 1:enable 0:disable rw 0 8 sabd internal mode select 1:class ab mode 0:class d mode rw 0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 39 7 ssen spread-spectrum enable 1: enable 0: disable rw 0 6 scen short-circuit protection enable 1: enable 0: disable rw 0 5 otpen over temperature protection enable 1:enable 0:disable rw 0 4 fben feedback enable 1: enable 0: disable rw 0 3 pen power stage enable 1: enable 0: disable rw 0 2 mute mute class d output 1: no mute 0: mute rw 0 1 cld2en class d2 enable 1: enable 0: disable rw 0 0 cld1en class d1 enable 1: enable 0: disable rw 0 classd_ctl1 class d control 1 register offset = 0xf bit(s) name description r/w reset 15:12 ?? (for analog future use) rw 0000 11:10 ssr spread-spectrum range 00:500~530k 3% 01:500~564k 6% 10:500~600k 9% 11:500~636k 12% rw 01 9:8 fix switch freq. select 00:385khz rw 00 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 40 fsen 01:450khz 10:600khz 11:750khz 7:6 nclpr non-clip range 00: 16cycle clipping 01: 32cycle clipping 10:48 cycle clipping 11:64 cycle clipping rw 01 5:4 edg output rise/fall edge 00:5ns 01:10ns 10:20ns 11:30ns rw 01 3:0 ibreg class d bias current select 0000 2ua 0001 0.5ua 0010 1ua 0100 4ua 1000 8ua other value is added by above. eq. set 0011, means 0.5ua+1ua=1.5ua rw 0000 classd_ctl2 class d control 2 register offset = 0x10 bit(s) name description r/w reset 15 ohwn2 class d 2 overheat warning state 0: normal 1: overheat r 0 14 scwn2 class d 2 short circuit warning state 0: normal 1: short circuit r 0 13 ohwn1 class d 1 overheat warning state 0: normal 1: overheat r 0 12 scwn1 class d 1 short circuit warning state 0: normal r 0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 41 1: short circuit 11:9 atime non-clip attack time select 000: 0.26ms/db 001: 0.5ms/db 010: 1.0ms/db 011: 2.0ms/db 100: 4.1ms/db 101: 8.2ms/db 110: 16.4ms/db 111: 32.8ms/db rw 011 8:6 rtime non-clip release time select 000: 16.4ms/db 001: 32.8ms/db 010: 0.07s/db 011: 0.13s/db 100: 0.26s/db 101: 0.52s/db 110: 1.05s/db 111: 2.1s/db rw 011 5:4 vrec[1 0] soft-clip recovery voltage / pout @ 4ohm 00: 1.8v , 180mw 01: 1.85v, 245mw 10: 1.9v, 320mw 11: 1.95v, 405mw rw 01 3:0 reserved reserved rw 0000 adc0_digitalctl adc0 digital control register offset=0x11 bits name description rw reset 15:12 - reserved r 0 11 ad0lr adc0l and adc0r added enable 0: disable1: enable note this bit is designed for karaoke use when this bit is ?1?; adc0l data and adc0r data are added and transformed to mcu rw 0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 42 10 ad0den adc0 digital debug enable 0: disable 1: enable rw 0 9:6 adgc0 adc0 digital gain control 0000: 0db 0001: 3db 0010: 6db 0011: 9db 0100: 12db 0101: 15db 0110: 18db 0111: 21db 1000: 24db 1001: 27db 1010: 30db 1011: 33db 1100: 36db 1101: 39db 1110: 42db 1111: 45db rw 0000 5 dcd dmic clock divide 0: div 4 1: div 2 (for voice recording) rw 0 4 dcen dmic clock enable 0: disable 1: enable rw 0 3 vren voice recording enable 0: disable 1: enable note: when voice recording is enable, bit 5 should be set to ?1?. rw 0 2 drfs dmic rising or falling edge sampling select 0: left channel sampling at rising edge right channel sampling at falling edge 1: left channel: sampling at falling edge right channel: sampling at rising edge rw 0 1 mlen dmic left filter enable 0: disable 1: enable w 0 0 dmren dmic right filter enable rw 0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 43 0: disable 1: enable note: when dmic is enable, adc0 should be disa ble, and when adc0 is enable, dmic should be disable. that is to say, when adc0_digitalctl bit [0] or bit [1] is ?1?, adc0_ctl bit [2] and bit [3] both should be set to ?0?, when adc0_ctl bit [2] or bit [3] is ?1?, adc0_digitalctl bit [0] and bit [1] both should be set to ?0?. when dmic left filter is enabl ed, the output of dmic right filter is zero, on the other hand, when dmic right filter is enabled, the output of dmic left filter is zero. adc0_hpfctl adc0 digital control register offset=0x12 bits name description rw reset 15:8 - reserved r 0 7:6 srsel0 sr select for removing wind noise filter0 00:8k/11.025k/12k 01:16k/22.05k/24k 10:32k/44.1k/48k 11:reserved rw 00 5:3 wnhpf0cut for wind noise filter0 cut off frequency, see figure 2.2.1 for details rw 000 2 hpf0dw select high pass filter0 for dc offset or wind noise 0: for dc offset 1: for wind noise rw 0 1 hpf0len high pass filter0 l enable 0 enable 1 disable rw 0 0 hpf0ren high pass filter0 r enable 0 enable 1 disable rw 0 adc0_ctl adc0 control register offset=0x13 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 44 bits name description rw reset 15 vmicinen internal mic powe r vmic control 0 disable 1 enable rw 0 14 fmlen fm input left channel enable; 0: disable 1: enable rw 0 13 fmren fm input right channel enable; 0: disable 1: enable rw 0 12:10 fmgain fm input gain control: 000 -3.0db 001 -1.5db 010 0.0db 011 1.5db 100 3.0db 101 4.5db 110 6.0db 111 7.5db rw 010 9 vmicexen external mic power vmic enabled 0 disabled 1 enabled rw 0 8:7 vmicexst external mic power vmic voltage setting 00 2.7v 01 2.9v 10 3.1v 11 3.2v rw 01 6 mic0len mic0 input l channel enabled 0 disable 1 enable rw 0 5 mic0ren mic0 input r channel enabled 0 disable 1 enable rw 0 4 mic0fdse mic0 input fully differential or single ended select 0 fd; 1 se; rw 0 3 ad0len adc0 left channel enable 0: disable 1: enable rw 0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 45 2 ad0ren adc0 right channel enable 0: disable 1: enable rw 0 1:0 adcis sigma-delta a/d0 input select: 00: select mic 01: select fm 10: select internal analog mixer output (aout) 11: reserved rw 01 agc0_ctl0 agc0 control register 0 offset = 0x14 ? bits name description rw reset 15:12 amp1g0l amp1 left channel gain select at agc0 disabled 0000: 16.5db 0001: 18db 0010: 19.5db 0011: 21db 0100: 22.5db 0101: 24db 0110: 25.5db 0111: 27db 1000: 28.5db 1001: 30db 1010: 31.5db 1011: 33db 1100: 34.5db 1101: 36db 1110: 37.5db 1111: 39db amp1 agc gain can be read out when agc0 is enabled, and can be written and read out when agc0 is disabled. rw 1001 11:8 amp1g0r amp1 right channel gain select at agc0 disabled 0000: 16.5db 0001: 18db 0010: 19.5db 0011: 21db 0100: 22.5db 0101: 24db 0110: 25.5db 0111: 27db 1000: 28.5db 1001: 30db 1010: 31.5db rw 1001 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 46 1011: 33db 1100: 34.5db 1101: 36db 1110: 37.5db 1111: 39db amp1 agc gain can be read out when agc0 is enabled, and can be written and read out when agc0 is disabled. 7 imicshd internal mic power controlled by external mic plug enable 0 disable 1 enable rw 0 6:3 - reserved for anal og future use rw 0110 2:0 amp0gr1 amp1 gain boost range select 000: +3db 001: +6db 010: +9db 011: +12db 100: +13.5db 101: +15db 110: +16.5db 111: +18db rw 011 agc0_ctl1 agc0 control 1 register offset=0x15 bits name description rw reset 15:13 - reserved for analog future use rw 000 12:10 ngt0 agc0 noise gate statistic time 000: 4*rmscy 001: 8*rmscy(1.36ms) 010: 16*rmscy 011: 32*rmscy 100: 64*rmscy 101: 128*rmscy 110: 256*rmscy 111: 512*rmscy rw 001 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 47 9:7 atkt0 agc0 attack(gain ramp-down) time for every gain step 000: 1*rmscy 001: 2*rmscy 010: 4*rmscy(683us) 011: 8*rmscy 100: 16*rmscy 101: 32*rmscy 110: 64*rmscy 111: 128*rmscy rw 010 6:4 dcyt0 agc0 decay(gain ramp-up) time for every gain step 000: 16*rmscy 001: 32*rmscy(5.46ms) 010: 64*rmscy 011: 128*rmscy 100: 256*rmscy 101: 512*rmscy 110: 1024*rmscy 111: 2048*rmscy rw 001 3:2 cmr0 agc0 rc filter cutoff frequency select 00 :207hz; 01: 414hz; 10 : 828hz; 11 : 1.65khz; rw 10 1:0 scy0 agc0 sense cycle select 00 :341us; 01: 683us 10 :1366us; 11 :2732us; rw 10 agc0_ctl2 agc0 control 2 register offset=0x16 bits name description rw reset free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 48 15:13 targl0 agc0 amp1 target level select at amp2gr=+6db 000: -42dbfs 001: -39dbfs 010: -36dbfs 011: -33dbfs 100: -30dbfs 101: -27dbfs 110: -24dbfs 111: -21dbfs rw 100 12:10 ngthsel0 agc0 noise gate threshold select at +28.5db gain peak sense 000: -27dbfs 001: -30dbfs 010: -33dbfs 011: -36dbfs 100: -39dbfs 101: -42dbfs 110: -45dbfs 111: -51dbfs rw 011 9 micaaen adc0 mic to pa path differential compensation enable 0: disable 1: enable rw 0 8 adben agc0 analog debug enabled(only for agc0) 0 disable 1 enable rw 0 7 rmsinsel0 agc0 sense input source select 0 left 1 right rw 0 6 - reserved for analog future use rw 1 5 ngslen0 agc0 noise gate maintain current gain or keep silence 0 maintain current gain 1 keep silence rw 0 4 ngten0 agc0 noise gate function enabled 0: disabled 1: enabled rw 0 3 zeroc0 agc0 gain change at zero-cross enabled 0: disabled 1: enabled rw 0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 49 2 gren0 agc0 gain_con gain reset function enabled 0: disabled 1:enabled rw 0 1 agc0len agc0 left channel enabled 0: disabled 1: enabled rw 0 0 agc0ren agc0 right channel enabled 0: disabled 1: enabled rw 0 adc_analog0 adc analog 0 register offset=0x17 bits name description rw default 15:13 ivsrmstn ivsrms bias tune 000 -25% 001 -18.75% 010 -12.5% 011 -6.25% 100 2ua 101 +6.25% 110 +12.5% 111 +18.75% rw 100 12 8 reserved for analog future use rw 00010 7 5 opbc1 the bias current select for opad1 in a/d: 000 3ua 001 4ua 010 5ua 011 6ua 100 7ua 101 8ua 100 9 ua 110 10 ua 111 11 ua rw 011 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 50 4:3 opbc23 the bias current select for opad2/3 in a/d: 00 2ua 01 3ua 10 4ua 11 5ua rw 01 2:0 vrdabc audio a/d voltage reference bias current select: 000 2ua 001 3ua 010 4ua ? 110 8ua 111 9ua rw 001 adc_analog1 adc analog 1 register offset=0x18 bits name description rw default 15:13 lpfbc audio a/d lpf bias current select: 000 3ua 001 3.5ua 010 4ua 011 4.5ua 100 5ua 101 5.5ua 110 6ua 111 6.5ua rw 100 12:11 lpfbufbc fd lpf buf op bias current select: 00 4ua 01 5ua 10 6ua 11 7ua rw 01 10 adcbias adc total bias tune 0 normal 1 +50% rw 0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 51 9:8 reserved for analog future use rw 01 7:6 fd1bc mic preamp fdop1 bias current select : 00 3ua 01 4ua 10 5ua 11 6ua rw 01 5:4 fd2bc mic preamp fdop2 bias current select : 00 2ua 01 3ua 10 4ua 11 5ua rw 01 3:2 fd1bufbc mic preamp fdop2 bias current select : 00 2ua 01 3ua 10 4ua 11 5ua rw 01 1:0 fmbc fm pre-amplifiers bias current select: 00 3ua 01 4ua 10 5ua 11 6ua rw 01 adc1_digitalctl adc1 digital control 1 register offset=0x19 bits name description rw reset 15 ad1lr adc1l and adc1r added enable 0: disable 1: enable note this bit is design ed for karaoke use when this bit is ?1?; adc1l data and adc1r data are added and transformed to mcu. rw 0 14 ad1den adc1 digital debug enable 0: disable 1: enable rw 0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 52 13:12 srsel0 sr select for removing wind noise filter1 00:48k/24k/12k 01:44.1k/22.05k/11.025k 10:32k/16k/8k 11:reserved rw 00 11:9 wnhpf1cut high pass filter1 for wind noise cut off frequency see figure 02-1 for details. rw 000 8 hpf1dw select high pass filter1 for dc offset or wind noise 0: for dc offset 1: for wind noise rw 0 7 hpf1en high pass filter1 l enable 0 enable 1 disable rw 0 6 hpf1en high pass filter1r enable 0 enable 1 disable rw 0 5:2 adgc1 adc1 digital gain control 0000: 0db 0001: 3db 0010: 6db 0011: 9db 0100: 12db 0101: 15db 0110: 18db 0111: 21db 1000: 24db 1001: 27db 1010: 30db 1011: 33db 1100: 36db 1101: 39db 1110: 42db 1111: 45db rw 0000 1:0 reserved rw 00 adc1_ctl adc1 control register offset=0x1a free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 53 bits name description rw reset 15:9 reserved for analog future use rw 0 8 vrda0en vrda output0 enable 0 disabled 1 enabled rw 0 7 vrda1en vrda output1 enable 0 disabled 1 enabled rw 0 6:5 reserved for analog future use rw 00 4 mic1len mic1 input l channel enabled 0 disable 1 enable rw 0 3 mic1ren mic1 input r channel enabled 0 disable 1 enable rw 0 2 mic1fdse mic1 input fully differential or single ended select 0 fd; 1 se; rw 0 1 ad1len adc1 l channel enable 0 disable 1 enable rw 0 0 ad1ren adc1 r channel enable 0 disable 1 enable rw 0 agc1_ctl0 agc1 control 0 register offset = 0x1b bits name description rw reset free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 54 15:12 amp1g1l amp1 left channel gain select at agc1 disabled when amp1grw=1 0000: 16.5db 0001: 18db 0010: 19.5db 0011: 21db 0100: 22.5db 0101: 24db 0110: 25.5db 0111: 27db 1000: 28.5db 1001: 30db 1010: 31.5db 1011: 33db 1100: 34.5db 1101: 36db 1110: 37.5db 1111: 39db amp1 agc gain can be read out when agc1 is enabled, and can be written and read out when agc1 is disabled. rw 1001 11:8 amp1g1r amp1 right channel gain select at agc1 disabled when amp1grw=1 0000: 16.5db 0001: 18db 0010: 19.5db 0011: 21db 0100: 22.5db 0101: 24db 0110: 25.5db 0111: 27db 1000: 28.5db 1001: 30db 1010: 31.5db 1011: 33db 1100: 34.5db 1101: 36db 1110: 37.5db 1111: 39db amp1 agc gain can be read out when agc1 is enabled, and can be written and read out when agc1 is disabled. rw 1001 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 55 7:3 - reserved for analog future use rw 00110 2:0 amp1gr1 amp1 gain boost range select 000: +3db 001: +6db 010: +9db 011: +12db 100: +13.5db 101: +15db 110: +16.5db 111: +18db rw 011 agc1_ctl1 agc1 control 2 register offset=0x1c bits name description rw reset 15:13 - reserved for analog future use rw 000 12:10 ngt1 agc1 noise gate statistic time 000: 4*rmscy 001: 8*rmscy(1.36ms) 010: 16*rmscy 011: 32*rmscy 100: 64*rmscy 101: 128*rmscy 110: 256*rmscy 111: 512*rmscy rw 001 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 56 9:7 atkt1 agc1 attack(gain ramp-down) time for every gain step 000: 1*rmscy 001: 2*rmscy 010: 4*rmscy(683us) 011: 8*rmscy 100: 16*rmscy 101: 32*rmscy 110: 64*rmscy 111: 128*rmscy rw 010 6:4 dcyt1 agc1 decay(gain ramp-up) time for every gain step 000: 16*rmscy 001: 32*rmscy(5.46ms) 010: 64*rmscy 011: 128*rmscy 100: 256*rmscy 101: 512*rmscy 110: 1024*rmscy 111: 2048*rmscy rw 001 3:2 cmr1 agc1 rc filter cutoff frequency select 00 :207hz; 01: 414hz; 10 : 828hz; 11 : 1.65khz; rw 10 1:0 scy1 agc1 sense cycle select 00 :341us; 01: 683us 10 :1366us; 11 :2732us; rw 10 agc1_ctl2 agc1 control 2 register offset=0x1d bits name description rw reset free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 57 15:13 targl1 agc1 amp1 target level select at amp2gr=+6db 000: -42dbfs 001: -39dbfs 010: -36dbfs 011: -33dbfs 100: -30dbfs 101: -27dbfs 110: -24dbfs 111: -21dbfs rw 100 12:10 ngthsel1 agc1 noise gate threshold select at +28.5db gain peak sense 000: -27dbfs 001: -30dbfs 010: -33dbfs 011: -36dbfs 100: -39dbfs 101: -42dbfs 110: -45dbfs 111: -51dbfs rw 011 9:8 - reserved for analog future use rw 00 7 rmsinsel1 agc1 sense input source select 0 left 1 right rw 0 6 - reserved for analog future use rw 1 5 ngslen1 agc1 noise gate1 maintain current gain or keep silence 0 maintain current gain 1 keep silence rw 0 4 ngten1 agc1 noise gate function enabled 0: disabled 1: enabled rw 0 3 zeroc1 agc1 gain change at zero-cross enabled 0: disabled 1: enabled rw 0 2 gren1 agc1 gain_con gain reset function enabled 0: disabled 1: enabled rw 0 1 agc1len agc1 left channel enabled 0: disabled 1: enabled rw 0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 58 0 agc1ren agc1 right channel enabled 0: disabled 1: enabled rw 0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 59 11. power supply & management subsystem 11.1 features atc260x pmu is a highly intergrated power management system. it supplies a solution for how to face the single chip lithium battery and the full power source which needs multipath power conversion output applications. atc260x pmu integrates 4 dcdc 12 ldo 2 load switch 10bit multiplex adc one linear charger self-adaption power distribution control unit etc, automatic monitoring power?s overvoltage, overcurrent, low-voltage, overtempreture etc abnormal conditions. dcdc1 work in buck mode input voltage range from 3.0v to 5.5v and the output voltage range from 0.7v to 1.4v the output voltage is adjustable with step of 25mv by setting the register the current limit is 1.2a.. dcdc2 work in buck mode input voltage range from 3.0v to 5.5v and the output voltage range from 1.3 to 2.2v the output voltage is adjustable with step of 50mv by setting the register the current limit is 1a. dcdc3 work in buck mode input voltage range from 3.0v to 5.5v and the output voltage range from 2.6 to 3.3v the output voltage is adjustable with step of 100mv by setting the register the current limit is 1a. dcdc4 work in boost mode with external most, input voltage range from 3.0v to 5.5v and the output voltage is 5v the current limit is 800ma ldo1 input is syspwr the output range is 2.6~3.3v adjusted 100mv per step and the current limit is 400ma ldo2 input is syspwr the output range is 2.6~3.3v adjusted, 100mv per step and the current limit is 200ma ldo3 input is syspwr or dc3out the output range is 1.5-2.0v adjusted,100mv per step and the current limit is 250ma ldo4 input issyspwr the output range is 2.8~3.5v adjusted 100mv per step and the current limit is 400ma ldo5 input is syspwr the output range is 2.6~3.3v adjusted 100mv per step and the current limit is150ma ldo6 input is syspwr or dc3out the output range is 0.7~1.4v adjusted 25mv per step and the current limit is 200ma ldo7 input issyspwr ordc3out the output range is 1.5~2.0v adjusted 100mv per step the current limit is 200ma free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 60 ldo8 input issyspwr the output range is 2.3~3.3v adjusted each rank is 100mv the current limit is 150ma ldo9 input issyspwr ordc3out the output range is 1.0~1.5v adjusted 100mv per step the current limit is 150ma ldo10 the output range is 2.3~3.3v adjusted 100mv per step the current limit is 100ma ldo11 input is syspwr the output range is 2.6~3.3v adjusted 100mv per step the current limit is 15ma used for io power of atc260x ldo12 the output range is 1.5~2.0v used for rtc. in standby mode. there are two switchs it can configure as ldo mode or switch mode. one current limit is 400ma and the other is 100ma one linear charge-management for li-ion battery, the max charge current is 1.5a it can adjust charging current automatically according to the current loading, includes trickle charge cc cv charging function, and it also has overcharge protection timing protection and etc. support backup battery charging. self-adaption power distribution control module, self-adaption control the power distribution, power seamless handover of bat vbus and wall to ensure stable power supply. the minimum standby current is lower than 25ua overcurrent and overvoltage protection function of each power, and overtempreture protection of ic. auxadc 10-bit, 16-channel analog-to-digital converters (adcs) input voltage range is 0-3v most circuit is used for monitoring the voltage, current and tempreture. 11.2 module description 11.2.1 block diagram free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 61 dc-dc1/buck 0.7-1.4v 1200ma dc-dc2/buck 1.3-2.15v 1000ma dc-dc3/buck 2.6-3.3v 1a dc-dc4/boost 5v 800ma ldo1 2.6-3.3v/400ma /psrr ldo1in ldo1out ldo2 2.6-3.3v/200ma/psrr ldo2in ldo2out ldo3 1.5-2.0v/250ma ldo3out ldo4 2.8-3.5v/400ma /psrr ldo4in ldo4out ldo5 2.6-3.3v/150ma/psrr ldo5in ldo5out ldo6 0.7-1.6v/200ma/psrr ldo6out core ddr i/o,nand,lcd usb host/hdmi 5v ldo7 1.5-2.0v/200ma/psrr ldo7out ldo8 2.3-3.3v/150ma/psrr ldo8in ldo8out switch1/ldo 400ma switch1_in switch1_out switch2/ldo 100ma switch2_in switch2_out apds syspwr bat usb_vbus wall_pwr backup_bat wallfet_en batfet_en battery charger backup battery charger vref vrefc refgnd ldo12 1.5-2.0v/5ma auxin0 auxin1 auxin2 auxin3 por por die tempeture power management onoff/reset ldo11 2.7-3.3v/15ma ldo9 1.0-1.5v/150ma/psrr ldo9out syspwr bat vbus wall_pwr backup_bat wkirq ldo10 2.3-3.3v/150ma/psrr ldo10out ldo10in 3 33 1 3 3 3 1 3331 1 11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 1 3 3 1 1 1 1 lowp lowp 1 aux adc 1 figure 0-1 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 62 11.2.2 dcdc module atc260x has four dcdc figure 0-2 atc260x buck dcdc circuit diagram three of these are buck dcdc dcdc1 generates 0.7~1.4v voltage to supply the master core?s need;dcdc2 generates 1.3~2.15v to supply the ddr?s need;dcdc3 generates 2.6~3.3v to supply the power for master control and atc260x?s io. all of three buck dcdc integrate mosfet inside, all of them are synchronization control, it can work normally only if installed one indu ctance and two capacitances outside. cin is a 10uf ceramic capacitor, and l is 2.2uh inductance, dcr<0.1ohm co=10uf ceramic capacitor buck dcdc efficiency curve is as follows free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 63 the other is asynchronous boost dcdc, it mainly supplies power for usb otg and hdmi,the maximum load capacity is 800ma, switch tube and fwd is external. dcdc4 peripheral connection as follows: gl5302 dc4drv dc4out dc4gnd l syspwr d c r load figure 0-3 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 64 11.2.3 ldo module atc260x has 12 ldo totally. the specifications as follows: input voltage(v) output voltage(v) max current(ma) input capacitance/output capacitance reference use ldo1 3~5.5 2.6~3.3 400 0.1uf/2.2uf master control avcc ldo2 3~5.5 2.6~3.3 200 0.1uf/2.2uf atc260xaudio+ethernet ldo3 3~5.5 1.5~2.0 250 0.1uf/2.2uf atc260x digital/sensor ldo4 3~5.5 2.8~3.5 400 0.1uf/2.2uf wifi+bluetooth ldo5 3~5.5 2.6~3.3 150 0.1uf/2.2uf sensor2.8v ldo6 3~5.5 0.7~1.4 200 0.1uf/2.2uf sata+mipi ldo7 3~5.5 1.5~2.0 200 0.1uf/2.2uf wifi1.8 ldo8 3~5.5 2.3~3.3 150 0.1uf/2.2uf fm+gps ldo9 3~5.5 1.0~1.5 150 0.1uf/2.2uf wifi1.2 ldo10 3~5.5 2.3~3.3 100 0.1uf/2.2uf sata2.5 ldo11 3-5.5 2.6~3.3 15 0.1uf/1.0uf svcc ldo12 3-5.5 1.5~2.0 5 0.1uf/1.0uf rtcvdd ldo has output overvoltage protection, output overcurrent protection and output low-voltage function. when the ldo output voltage be yond the overvoltage protection range, ldo will overvoltage suspend,and whether ldo overvoltage enabled,it all depends on register. when ldo output voltage lower than low-voltage protection, ldo low-protection suspend will be sent out, and whether ldo low-voltage enabled, it all depends on register. 11.2.4 switch module atc260x has two switches. switch1 is used in generating the sd card power, its input is dc3out,the current limit is 400ma. and,switch1 can be config as ldo. when choose ldo mode, ldo output 3.0~3.3v, in that mode, its input usually chooses syspwr. switch2 input is dc3out its current limit is 100ma switch2 can also be config as ldo, when choose ldo mode, ldo output 1.0~3.3v,in that mode , its input usually selects syspwr. free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 65 11.2.5 charger module atc260x integrates a constant current/constant voltage charger. it can adjust the charging current by power dissipation. it also has battery detecting and trickle charging function. when insert a external adaptor,and detecting th e syspwr voltage is higher than bat,the charger will enabled by software and the atc260x pmu can config charging process automatically. atc260x pmu dectects whether the battery is exist or not depend on the bat pin voltage. charge current can set by register, the max current is 1.5a. the reality charging current can read by charging current adc register. in process of charging,the ic inner tempreture and battery tempreture is monitored all the time, if the tempreture is higher or lower than the standard value,suspend signal will send, software is going to take measures and charging paused. measuring battery s tempreture by temp pin. figure 0-4 atc260x battery tempreture detecting diagram atc260x supports backup battery charging, when the master battery powered down,backup battery can supply rtc power and save the time and other information of system. you can choose li-ion battery or 3v button battery as backup battery and the charging current can be set. 11.2.6 apds module free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 66 figure 0-5 atc260x apds adaptive power distribute system block diagram as shown above. atc260x pmu get power from bat vbus and wall.syspwr is a public taking power node, both dcdc and ldo take power from this node. vbus connects to syspwr through ic internal ideal diode(id). in order to avoide vbus current flowing to syspwr in otg application, the id from vbus to suspwr has an enabled control.when the id is disable, vbus and syspwr will be cut off completely. atc260xpmu needs to provide large power, in order to reduce circuit heat loss,two external mos is necessery , which as the block diagram show pmos1 and pmos2. in ic between bat and syspwr,there is a ideal diode, the same as wall and syspwr. atc260x can detect bat vbus wall and syspwr voltage at the same time. it also can detect current which flows to ideal diode. when bat output voltage beyond setting, it will send bat overvoltage suspend. when bat voltage lower than setting, it will send bat low-voltage suspend. when bat current beyond setting, it will send bat overcurrent suspend; when bat current beyond overcurrent shut-off setting, the power will be force to shut off to protect ic. when vbus voltage higher than settings, it will send vbus overvoltage suspend. when vbus free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 67 voltage lower than settings, it will send vbus low-voltage suspend. when vbus current beyond setting, it will send vbus overcurrent suspend. when vbus current beyond overcurrent shut-off setting, it also will force to shut off power to protect ic. when wall voltage higher than setting, it will send wall overvoltage suspend. when wall voltage lower than setting, it will send wall low-voltage suspend. when wall current beyond setting, it will send wall overcurrent suspend. when wall current beyond overcurrent shut-off setting, it will also force to shut off power to protect ic. when syspwr voltage higher than setting, it will send syspwr overvoltage suspend. 11.2.7 standby module according to the application, the power states is divided as follows: s1- working mode in s1 master can work normally, and its kernel and io can also operate normally, that is to say, both dcdc1 and dcdc3 work regularl y and communicate with atc260x normally. ldo6 and ldo1 needed by the corresponding master should be work normally. this state called s1. s2- standby mode when both master ic s kernel and io shut off, its essential in formation saves in ddr so that start fast. at this time, dcdc2 work normally, master and atc260x can not communicate. we called this state s2. s3-sleep mode when we don t use it in a long time, ddr apparatus also can shut off to enter s3 state. s4- deep sleep mode when standby power dissipation is minimum, entering s4 state. wakeup elements: atc260x has the following wakeup elements: onoff button alarm tp wkirq reset rem_con vbus wall hdsw ir in s2 all wakeup elements can wake up. in s3 all wakeup elements can wake up. in s4 only exist rtcvdd svcc shut off so wkirq tp rem_con ir can not wake up the other wakeup elements can wake up. either long or short press onoff button can wake up,it all depends on register. in s1 software can configurate into s2 s3 or s4 by setting the en_s1 en_s2 en_s3 bits as follow. free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 68 power state en_s1 en_s2 en_s3 s4 0 0 0 s3 0 0 1 s2 0 1 x s1 1 x x when in s1 mode, it is need to enter s2, we can configure en s2=1 first, then write 0 to en_s1, it will enter s2 state. overcurrent protection if ldo1 ldo2 ldo3 or ldo6 is overcurrent, then pull down pwrok, and entering standby state according to en_s2, en_s3. if bat wall or vbus overcurrent, and it is enabled to its corresponding overcurrent shutoff, then entering standby state according to en_s2 and en_s3 overtempreture protection when ic is overtempreture, and the overtempreture protect is enabled, then entering standby state by en_s2 and en_s3. free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 69 11.2.8 por and power on/off sequence module figure 0-6 power on sequence atc260x power on process is to turn on the power of bat or wall or vbus, then generating rtcvdd and svcc. after that, atc260x?s 1.8v kernel voltage and master?s kernel 1.0v voltage will be produced. then generating atc260x and master?s high-voltage part. at last, when all the power is stable, sending por to master, it can start to run. if it is software powered down, master sends order to atc260x, and atc260x receiving the order to pull down the pwrok and por, then shut off dcdc1 dcdc3 ldo1 ldo2 ldo3 and ldo6 if it is force to power down, the atc260x will pull down pwrok and por when it detects any of signals of dc1outok dc3outok ldo1outok ldo2outok ldo3outok and ldo6outok is pulled down. free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 70 11.2.9 onoff&reset module figure 0-7 in the atc260x pmu,onoff and reset multiplex the same pin, as shown above. the sysrst or sysonoff signal will be generated by the voltage at the pin, it is sent to handle by corresponding circuit. if pressing reset and onoff button at the same time, it will reset all registers in rtcvdd voltage region. when long press onoff button beyond the setting time 6s 8s 10s 12s, it will send the same signal as p_reset to reset the whole system. 11.3 register list pmu block address name base address pmu 0x0000 table 0-1 pmu controller registers offset register name description 0x00 pmu_sys_ctl0 pmu system control register0 0x01 pmu_sys_ctl1 pmu system control register1 0x02 pmu_sys_ctl2 pmu system control register2 0x03 pmu_sys_ctl3 pmu system control register3 0x04 pmu_sys_ctl4 pmu system control register4 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 71 0x05 pmu_sys_ctl5 pmu system control register5 0x06 pmu_sys_ctl6 pmu system control register6 0x07 pmu_sys_ctl7 pmu system control register7 0x08 pmu_sys_ctl8 pmu system control register8 0x09 pmu_sys_ctl9 pmu system control register9 0x0a pmu_bat_ctl0 pmu bat control register0 0x0b pmu_bat_ctl1 pmu bat control register1 0x0c pmu_vbus_ctl0 pmu vbus control register0 0x0d pmu_vbus_ctl1 pmu vbus control register1 0x0e pmu_wall_ctl0 pmu wall control register0 0x0f pmu_wall_ctl1 pmu wall control register1 0x10 pmu_sys_pending pmu sy stem pending register 0x11 pmu_dc1_ctl0 pmu dcdc1 control register0 0x12 pmu_dc1_ctl1 pmu dcdc1 control register1 0x13 pmu_dc1_ctl2 pmu dcdc1 control register2 0x14 pmu_dc2_ctl0 pmu dcdc2 control register0 0x15 pmu_dc2_ctl1 pmu dcdc2 control register1 0x16 pmu_dc2_ctl2 pmu dcdc2 control register2 0x17 pmu_dc3_ctl0 pmu dcdc3 control register0 0x18 pmu_dc3_ctl1 pmu dcdc3 control register1 0x19 pmu_dc3_ctl2 pmu dcdc3 control register2 0x1a pmu_dc4_ctl0 pmu dcdc4 control register0 0x1b pmu_dc4_ctl1 pmu dcdc4 control register1 0x1e pmu_ldo1_ctl pmu ldo1 control register 0x1f pmu_ldo2_ctl pmu ldo2 control register 0x20 pmu_ldo3_ctl pmu ldo3 control register 0x21 pmu_ldo4_ctl pmu ldo4 control register 0x22 pmu_ldo5_ctl pmu ldo5 control register 0x23 pmu_ldo6_ctl pmu ldo6 control register 0x24 pmu_ldo7_ctl pmu ldo7 control register 0x25 pmu_ldo8_ctl pmu ldo8 control register 0x26 pmu_ldo9_ctl pmu ldo9 control register 0x27 pmu_ldo10_ctl pmu ldo10 control register 0x28 pmu_ldo11_ctl pmu ldo11 control register 0x29 pmu_switch_ctl pmu switch control register 0x2a pmu_ov_ctl0 pmu over voltage control register0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 72 0x2b pmu_ov_ctl1 pmu over voltage control register1 0x2c pmu_ov_status pmu over voltage status register 0x2d pmu_ov_en pmu over voltage detect enable register 0x2e pmu_ov_int_en pmu over voltage int enable register 0x2f pmu_oc_ctl pmu over current control register 0x30 pmu_oc_status pmu over current status register 0x31 pmu_oc_en pmu over current detect enable register 0x32 pmu_oc_int_en pmu over current int enable register 0x33 pmu_uv_ctl0 pmu under voltage control register0 0x34 pmu_uv_ctl1 pmu under voltage control register1 0x35 pmu_uv_status pmu under voltage status register 0x36 pmu_uv_en pmu under voltage detect enable register 0x37 pmu_uv_int_en pmu under voltage int enable register 0x38 pmu_ot_ctl pmu over tem perture control register 0x39 pmu_charger_ctl0 pmu charger control register0 0x3a pmu_charger_ctl1 pmu charger control register1 0x3b pmu_charger_ctl2 pmu charger control register2 0x3c pmu_bakcharger_ctl pmu bakcharger control register 0x3d pmu_apds_ctl pmu apds control register 11.4 register description 11.4.1 pmu_sys_ctl0 pmu_sys_ctl0 register default 0xe055 offset = 0x00 bit(s) name description r/w reset 15 usb_wk_en vbus wake up enable 1 vbus beyond the setting voltage can wake up 0 vbus beyond the setting voltage cannot wake up r/w 0x1 14 wall_wk_en wall wake up enable 1 wall beyond the setting voltage can wake up r/w 0x1 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 73 0 wall beyond the setting voltage cannot wake up 13 onoff_long_wk_en onoff long press to wake up enable 1 onoff long press can wake up 0 onoff long press cannot wake up r/w 0x1 12 onoff_short_wk_en onoff short press wake up enable 1 onoff short press can wake up 0 onoff short press cannot wake up r/w 0x0 11 wkirq_wk_en wkirq wake up enable 1 wkirq can wake up 0 wkirq cannot wake up r/w 0x0 10 tp_wk_en tp wake up enable 1 tp touch can wake up 0 tp touch cannot wake up r/w 0x0 9 rem_con_wk_en rem_con wake up enable 1 rem_con button can wake up 0 rem_con button cannot wake up r/w 0x0 8 alarm_wk_en alarm wake up enable 1 alarm can wake up 0 alarm cannot wake up r/w 0x0 7 hdsw_wk_en hard switching wake enable 0 no 1 yes r/w 0x0 6 reset_wk_en reset wake up enable 0 no 1 yes r/w 0x1 5 ir_wk_en ir wake up enable 0 no 1 yes r/w 0x0 4:3 vbus_wk_th vbus wake up threshold 00 4.05v 01 4.2v 10 4.35v 11 4.5v r/w 10 2:1 wall_wk_th wall wake up threshold 00 4.05v 01 4.2v 10 4.35v 11 4.5v r/w 10 0 onoff_muxkey_en onoff multiplex button enable r/w 0x1 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 74 0 disable no preset button 1 enable have preset button 11.4.2 pmu_sys_ctl1 pmu_sys_ctl1 register default 0x000e offset = 0x01 bit(s) name description r/w reset 15 usb_wk_flag vbus wake up flag 1 vbus wake up happened 0 no vbus wake up r 0x0 14 wall_wk_ flag wall wake up flag 1 wall wake up happen 0 no wa l l wake up r 0x0 13 onoff_long_wk_ flag onoff long press button wake up flag 1 long press onoff button to wake up happened 0 not long press onoff button to wake up r 0x0 12 onoff_short_wk_ flag onoff press button to wake up 1 long press onoff to wake up happened 0 no long press onoff to wake up r 0x0 11 wkirq_wk_ flag wkirq wake up flag 1 wkirq wake up happened 0 not wkirq to wake up r 0x0 10 tp_wk_ flag tp wake up flag 1 tp wake up happened 0 not tp to wake up r 0x0 9 rem_con_wk_ flag rem_con wake up flag 1 rem_con to wake up happened 0 not rem_con to wake up r 0x0 8 alarm_wk_ flag alarm wake up flag 1 alarm to wake up happened 0 not alarm to wake up r 0x0 7 hdsw_wk_ flag hdsw wake up flag 1 hdsw to wake up happened 0 not hdsw to wake up r 0x0 6 reset_wk_ flag reset wake up flag r 0x0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 75 1 reset to wake up happened 0 not reset to wake up 5 ir_wk_ flag ir wake flag 1 ir to wake up happened 0 not ir to wake up r 0x0 4:3 lb_s4 low power to enter s4 voltage setting 00 2.9v 01 3.0v 10 3.1v 11 3.3v system is in s1 s2 s3 when bat voltage lower than the settings, and there?s no usb and wall, entering s4 mode directly r/w 01 2 lb_s4_en low power entering s4 enable(it contains detecting enable) 0 disable 1 enable r/w 0x1 1 enrtcosc internal 32k clock enable 0 disable 1 enable r/w 0x1 0 en_s1 entering s1 state enable 0 no entering s1 1 entering s1 r/w 0x0 11.4.3 pmu_sys_ctl2 pmu_sys_ctl2 register default 0x0680 offset = 0x02 bit(s) name description r/w reset 15 onoff_press whether onoff button is pressed 0 onoff is not pressed 1 onoff is pressed r 0x0 14 onoff_short_press onoff short press pending 0: no short press onoff button 1: short press onoff button write 1 clear 0 r/w 0x0 13 onoff_long_press onoff long press pending 0: no long press onoff button r/w 0x0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 76 1: long press onoff button write 1 clear 0 12 onoff_int_en onoff suspend enbale 0 disable 1 enable r/w 0x0 11:10 onoff_press_time onoff setting by time of press button 00: 60ms < t < 0.5s, judged as short press; t >=0.5s, judged as long press; 01: 60ms < t < 1s, judged as short press; t >=1s, judged as long press; 10: 60ms < t < 2s, judged as short press; t >=2s, judged as long press; 11: 60ms < t < 4s, judged as short press; t >=4s, judged as long press; r/w 01 9 onoff_reset_en onoff long press reset function enable 0 disable 1 enable r/w 1 8 7 onoff_reset_time_sel long press onoff and send reset time selection 00 6s 01 8s 10 10s 11 12s r/w 01 6 s2_timer_en s2_timer_en 0:disable 1:eanbel when s2timer enabled entering s2 s2timer starts to time, when time to the settings, entering s3 r/w 0x0 5 3 s2timer s2timer 000 6min 001 16min 010 31min 011 61min 100 91min 101 121min 110 151min 111 181min r/w 0x0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 77 2:0 reserved reserved r/w 0x0 11.4.4 pmu_sys_ctl3 pmu_sys_ctl3 register default 0x0000 offset = 0x03 bit(s) name description r/w reset 15 en_s2 entering s2 state enable 0 no entering s2 1 entering s2 r/w 0x0 14 en_s3 entering s3 state enbale 0 no entering s3 1 entering s3 r/w 0x0 13 s3_timer_en s3_timer_en 0:disable 1:eanbel when s3timer enabled, enting s3 s3timer starts to time, when time to the settings, entering s4 r/w 0x0 12 10 s3timer s3timer 000 6min 001 16min 010 31min 011 61min 100 91min 101 121min 110 151min 111 181min r/w 0x0 9 4 reserved reserved r/w 0x0 3 ir_pin_type configure ir pin for different functions 0 ir 1 gpio r/w 0 2 ir _gpio_output_en configure ir pin?s gpio to output enable 0 disable 1 enable r/w 0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 78 1 ir _gpio_intput_en configure ir?s gpio to input enable 0 disable 1 enable r/w 0 0 ir_gpio_data ir?s gpio data r/w 0 11.4.5 pmu_sys_ctl4 pmu_sys_ctl4 register default 0x0080 offset = 0x04 bit(s) name description r/w reset 15 wkirq_pin_type configure wkirq pin for different functions 0 wkirq 1 gpio r/w 0 14 wkirq_gpio_output_en configure wkirq?s gpio output enable 0 disable 1 enable r/w 0 13 wkirq_gpio_intput_en configure wkirq?s gpio to output enable 0 disable 1 enable r/w 0 12 wkirq_gpio_data wkirq?s gpio data r/w 0 11 10 wkirq_tpye wkirq?s type 00 high level active 01 low level active 10 rising edge- triggered 11 falling edge-triggered r/w 00 9 wkirq_32k_en configure wkirq pin to send out 32k clock 0 wkirq?s function is defined by bit15 1 wkirq send out 32k clock r/w 0x0 8 reserved reserved r/w 0x0 7 lowp _gpio_output_en configure lowp?s gpio to output enable 0 disable 1 enable r/w 1 6 lowp _gpio_intput_en configure lowp?s gpio to input r/w 0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 79 enable 0 disable 1 enable 5 lowp _gpio_data lowp gpio data r/w 0 4 lowp_32k_en configure lowp pin to send out 32k clock 0 lowp make gpio 1 lowp send out 32k clock r/w 0x0 3 2 reserved reserved r/w 0x0 1 wkirq_en wkirq interrupt enable 0: disable 1: enable r/w 0 0 wkirq_pd wkirq pending 0 wkirq is not active 1 wkirq is active write 1 clear 0 r/w 0 11.4.6 pmu_sys_ctl5 pmu_sys_ctl5 register default 0x0180 offset = 0x05 bit(s) name description r/w reset 15 1 reserved reserved r/w 0x0 10 tp_dect_en tp wake up detecting enable 0: disable 1:enable r/w 0 9 remcon_dect_en remcon wake up detecting enable 0: disable 1:enable r/w 0 8 vbuswkdten vbus wakeup detect enable 0: disable 1:enable r/w 1 7 wallwkdten wall wakeup detect enable 0: disable 1:enable r/w 1 6 0 reserved reserved r/w 0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 80 11.4.7 pmu_sys_ctl6 pmu_sys_ctl6 register default 0x0000 offset = 0x06 bit(s) name description r/w reset 15 0 reserved reserved r/w 0x0 11.4.8 pmu_sys_ctl7 pmu_sys_ctl7 register default 0x0000 offset = 0x07 bit(s) name description r/w reset 15 0 reserved reserved r/w 0x0 11.4.9 pmu_sys_ctl8 pmu_sys_ctl8 register default 0x0000 offset = 0x08 bit(s) name description r/w reset 15 0 reserved no reset by preset and onoffreset r/w 0x0 11.4.10pmu_sys_ctl9 pmu_sys_ctl9 register default 0x0000 offset = 0x09 bit(s) name description r/w reset 15 0 reserved no reset by preset and onoffreset r/w 0x0 11.4.11 pmu_bat_ctl0 pmu_bat_ctl0 register default 0x5680 offset = 0x0a free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 81 bit(s) name description r/w reset 15 14 bat_uv_vol bat undervoltage suspend voltage setting 00 3.1v 01 3.3v 10 3.4v 11 3.5v r/w 01 13:12 bat_ov_vol bat overvoltage suspend voltage setting 00 4.3v 01 4.4v 10 4.5v 11 4.8v r/w 01 11:8 bat_oc_set bat overcurrent susp end current setting 0000 200ma 0001 250ma 0010 300ma 0011 350ma 0100 400ma 0101 450ma 0110 500ma 0111 550ma 1000 600ma 1001 650ma 1010 700ma 1011 750ma 1100 800ma 1101 850ma 1110 900ma 1111 950ma the detecting current is flowing from bat to syspwr ideal diode overcurrent signal debounce 1ms r/w 0110 7 6 bat_oc_ shutoff _set bat ouvercurrent shutoff current setting 00 600ma 01 800ma 10 1000ma 11 1200ma overcurrent signal debounce 1ms r/w 10 5 0 reserved reserved r/w 0x0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 82 11.4.12 pmu_bat_ctl1 pmu_bat_ctl1 register default 0xfc00 offset = 0x0b bit(s) name description r/w reset 15 bat_oc_en bat overcurrent detect enable 0 disable 1 enable r/w 1 14 bat_ov_en bat overvoltage detect enable 0 disable 1 enable r/w 1 13 bat_uv_en bat undervoltage detect enable 0 disable 1 enable r/w 1 12 bat_oc_int_en bat overcurrent suspend enable 0 disable 1 enable r/w 1 11 bat_ov_int _en bat overvoltage suspend enable 0 disable 1 enable r/w 1 10 bat_uv_int _en bat undervoltage suspend enable 0 disable 1 enable r/w 1 9 bat_oc_shutoff_en bat overcurrent shutoff enable 0 disable 1 enable r/w 0 8 0 reserved reserved r/w 0x0 11.4.13 pmu_vbus_ctl0 pmu_vbus_ctl0 register default 0xa680 offset = 0x0c bit(s) name description r/w reset 15 14 vbus_uv_vol vbus undervoltage suspend voltage setting 00 3.8v r/w 10 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 83 01 4.0v 10 4.3v 11 4.5v 13:12 vbus_ov_vol vbus overvoltage suspend voltage setting 00 5.3v 01 5.5v 10 5.6v 11 5.8v r/w 10 11:8 vbus_oc_set vbus overcurrent suspend voltage setting 0000 100ma 0001 500ma 0010 600ma 0011 700ma 0100 800ma 0101 900ma 0110 1000ma others reserved the detecting current is flowing from bat to syspwr ideal diode overcurrent signal debounce 1ms r/w 0110 7 6 vbus_oc_ shutoff _set vbus overcurrent shutoff current setting 00 600ma 01 800ma 10 1000ma 11 1200ma overcurrent signal debounce 1ms r/w 10 5 0 reserved reserved r/w 0x0 11.4.14 pmu_vbus_ctl1 pmu_vbus_ctl1 register default 0xfc00 offset = 0x0d bit(s) name description r/w reset 15 vbus_oc_en vbus overcurrent detecting enable 0 disable 1 enable r/w 1 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 84 14 vbus_ov_en vbus overvoltage detecting enable 0 disable 1 enable r/w 1 13 vbus_uv_en vbus undervoltage detecting enable 0 disable 1 enable r/w 1 12 vbus_oc_int_en vbus overcurrent suspend enable 0 disable 1 enable r/w 1 11 vbus_ov_int _en vbus overvoltage suspend enable 0 disable 1 enable r/w 1 10 vbus_uv_int _en vbus undervoltage suspend enable 0 disable 1 enable r/w 1 9 vbus_oc_shutoff_en vbus overcurrent shutoff enable 0 disable 1 enable r/w 0 8 0 reserved reserved r/w 0x0 11.4.15 pmu_wall_ctl0 pmu_wall_ctl0 register default 0xe680 offset = 0x0e bit(s) name description r/w reset 15 14 wall_uv_vol wall undervoltage suspend voltage setting 00 3.8v 01 4.0v 10 4.3v 11 4.5v r/w 11 13:12 wall_ov_vol wall overvoltage suspend voltage setting 00 5.3v 01 5.5v 10 5.6v 11 5.8v r/w 10 11:8 wall_oc_set wall overcurrent suspend current r/w 0110 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 85 setting 0000 200ma 0001 250ma 0010 300ma 0011 350ma 0100 400ma 0101 450ma 0110 500ma 0111 550ma 1000 600ma 1001 650ma 1010 700ma 1011 750ma 1100 800ma 1101 850ma 1110 900ma 1111 950ma the detecting current is flowing from bat to syspwr ideal diode overcurrent signal debounce 1ms 7 6 wall_oc_ shutoff _set wall overcurrent shutoff current setting 00 600ma 01 800ma 10 1000ma 11 1200ma overcurrent signal debounce 1ms r/w 10 5 0 reserved reserved r/w 0x0 11.4.16 pmu_wall_ctl1 pmu_wall_ctl1 register default 0xfc00 offset = 0x0f bit(s) name description r/w reset 15 wall_oc_en wall overcurrent detect enable 0 disable 1 enable r/w 1 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 86 14 wall_ov_en wall overvoltage detect enable 0 disable 1 enable r/w 1 13 wall_uv_en wall undervoltage detect enable 0 disable 1 enable r/w 1 12 wall_oc_int_en wall overcurrent suspend enable 0 disable 1 enable r/w 1 11 wall_ov_int _en wall overvoltage suspend enable 0 disable 1 enable r/w 1 10 wall_uv_int _en wall undervoltage suspend enable 0 disable 1 enable r/w 1 9 wall_oc_shutoff_en wall overcurrent shutoff enable 0 disable 1 enable r/w 0 8 0 reserved reserved r/w 0x0 11.4.17 pmu_sys_pending pmu_sys_pending register default 0x0000 offset = 0x10 bit(s) name description r/w reset 15 bat_ov_status bat overvoltage state indication 0 present bat votage is not overvoltage 1 present bat voltage is overvotage r 0x0 14 bat_uv_status bat undervoltage state indication 0 present bat votage is not undervoltage 1 present bat voltage is undervotage r 0x0 13 bat_oc_status bat overcurrent state indication 0 present bat current is not overcurrent r 0x0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 87 1 present bat current is overcurrent 12 vbus_ov_status vbus overvoltage state indication 0 present bat votage is not overvoltage 1 present bat voltage is overvotage r 0x0 11 vbus _uv_status vbus undervoltage state indication 0 present bat votage is not undervoltage 1 present bat voltage is undervotage r 0x0 10 vbus _oc_status vbus overcurrent state indication 0 present bat current is not overcurrent 1 present bat current is overcurrent r 0x0 9 wall_ov_status wall overvoltage state indication 0 present bat votage is not overvoltage 1 present bat voltage is overvotage r 0x0 8 wall _uv_status wall undervoltage state indication 0 present bat votage is not undervoltage 1 present bat voltage is undervotage r 0x0 7 wall _oc_status wall overcurrent state indication 0 present bat current is not overcurrent 1 present bat current is overcurrent r 0x0 6 1 reserved reserved r/w 0x0 0 status_clear1 status indicator clear bit write 1 to this bit, and the register bit15~7 will be cleared. after clearing, this bit turn to 1 automatically r/w 0x0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 88 11.4.18 pmu_dc1_ctl0 pmu_dc1_ctl0 register default 0x8629 offset = 0x11 bit(s) name description r/w reset 15 12 reserved reserved r/w 1000 11-7 dc1_vol dc1(vdd) voltage setting 00000:0.700v 00001:0.725v ?? 01100:1.00v ?? 11100:1.40v others:reserved dcdc1_voltage=0.7v+ dcdc1_vol*25mv r/w 01100 6 0 reserved reserved r/w 0101001 11.4.19 pmu_dc1_ctl1 pmu_dc1_ctl1 register default 0xecae offset = 0x12 bit(s) name description r/w reset 15 0 reserved reserved r/w 1110110010101110 11.4.20 pmu_dc1_ctl2 pmu_dc1_ctl1 register default 0x334b offset = 0x13 bit(s) name description r/w reset 15: 0 reserved reserved r/w 0011001101001011 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 89 11.4.21 pmu_dc2_ctl0 pmu_dc2_ctl0 register default 0x088b offset = 0x14 bit(s) name description r/w reset 15 dc2_en dcdc2 enable r/w 0 14-12 reserved reserved r/w 000 11-8 dc2_vol dcdc2voltage setting 0000:1. 3 0v 0001:1. 3 5v 0010:1.40v 0011:1.45v 0100:1.50v 0101:1.55v 0110:1.60v 0111:1.65v 1000:1.70v 1001:1.75v 1010:1.80v 1011:1.85v 1100:1.90v 1101:1.95v 1110:2.05v 1111:2.15v r/w 1000 7 0 reserved reserved r/w 1000101 11.4.22 pmu_dc2_ctl1 pmu_dc2_ctl1 register default 0xecae offset = 0x15 bit(s) name description r/w reset 15 0 reserved reserved r/w 1110110010101110 11.4.23 pmu_dc2_ctl2 pmu_dc2_ctl1 register default 0x334b free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 90 offset = 0x16 bit(s) name description r/w reset 15: 0 reserved reserved r/w 0011001101001011 11.4.24 pmu_dc3_ctl0 pmu_dc3_ctl0 register default 0x8b8b offset = 0x17 bit(s) name description r/w reset 15-12 reserved reserved r/w 1000 11-9 dc3_vol dcdc3 voltage setting 000:2.6v 001:2.7v 010:2.8v 011:2.9v 100:3.0v 101:3.1v 110:3.2v 111:3.3v r/w 101 8 7 en_setvcc select working circuit 00 ldo mode work 01 dcdc mode work 1x ldo mode work r/w 11 6 0 reserved reserved r/w 0001011 11.4.25 pmu_dc3_ctl1 pmu_dc3_ctl1 register default 0xe52e offset = 0x18 bit(s) name description r/w reset 15 0 reserved reserved r/w 1110010100101110 11.4.26 pmu_dc3_ctl2 pmu_dc3_ctl1 register default 0x334b free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 91 offset = 0x19 bit(s) name description r/w reset 15: 0 reserved reserved r/w 0011001100001011 11.4.27 pmu_dc4_ctl0 pmu_dc4_ctl0 register default 0x81f4 offset = 0x1a bit(s) name description r/w reset 15 1 reserved reserved r/w 100000011111010 0 dc4_en dcdc4 enable bit 0 disable 1 enable r/w 0 11.4.28 pmu_dc4_ctl1 pmu_dc4_ctl1 register default 0x0000 offset = 0x1b bit(s) name description r/w reset 15 0 reserved reserved r/w 00 11.4.29 pmu_ldo1_ctl pmu_ldo1_ctl register default 0xa000 offset = 0x1e bit(s) name description r/w reset 15-13 ldo1_vol ldo1 voltage setting 000:2.6v 001:2.7v 010:2.8v 011:2.9v 100:3.0v 101:3.1v 110:3.2v r/w 101 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 92 111:3.3v 12-0 reserved reserved r/w 0 11.4.30 pmu_ldo2_ctl pmu_ldo2_ctl register default 0xa000 offset = 0x1f bit(s) name description r/w reset 15 13 ldo2_vol ldo2 voltage setting 000:2.6v 001:2.7v 010:2.8v 011:2.9v 100:3.0v 101:3.1v 110:3.2v 111:3.3v r/w 101 12 0 reserved reserved r/w 0 11.4.31 pmu_ldo3_ctl pmu_ldo3_ctl register default 0x6000 offset = 0x20 bit(s) name description r/w reset 15 13 ldo3_vol ldo3 voltage setting 000:1.5v 001:1.6v 010:1.7v 011:1.8v 100:1.9v 101:2.0v others:reserved r/w 011 12 0 reserved reserved r/w 0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 93 11.4.32pmu_ldo4_ctl pmu_ldo4_ctl register default 0x6000 offset = 0x21 bit(s) name description r/w reset 15 13 ldo4_vol ldo4 voltage setting 000:2.8v 001:2.9v 010:3.0v 011:3.1v 100:3.2v 101:3.3v 110:3.4v 111:3.5v r/w 011 12 1 reserved reserved r/w 0 0 ldo4_en ldo4 enable bit 0 disable 1 enable r/w 0 11.4.33 pmu_ldo5_ctl pmu_ldo5_ctl register default 0x4000 offset = 0x22 bit(s) name description r/w reset 15 13 ldo5_vol ldo5 voltage setting 000:2.6v 001:2.7v 010:2.8v 011:2.9v 100:3.0v 101:3.1v 110:3.2v 111:3.3v r/w 010 12 1 reserved reserved r/w 0 0 ldo5_en ldo5 enable bit r/w 0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 94 0 disable 1 enable 11.4.34 pmu_ldo6_ctl pmu_ldo6_ctl register default 0x6000 offset = 0x23 bit(s) name description r/w reset 15 11 ldo6_vol ldo6 voltage setting 00000:0.700v 00001:0.725v ?? 01100:1.00v ?? 11100:1.40v others:1.40v ldo6_voltage=0.7v+ ldo6_vol*25mv r/w 01100 10 0 reserved reserved r/w 0 11.4.35 pmu_ldo7_ctl pmu_ldo7_ctl register default 0x6000 offset = 0x24 bit(s) name description r/w reset 15 13 ldo7_vol ldo7 voltage setting 000:1.5v 001:1.6v 010:1.7v 011:1.8v 100:1.9v 101:2.0v others:2.0v r/w 011 12 1 reserved reserved r/w 0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 95 0 ldo7_en ldo7 enable bit 0 disable 1 enable r/w 0 11.4.36 pmu_ldo8_ctl pmu_ldo8_ctl register default 0x8000 offset = 0x25 bit(s) name description r/w reset 15 12 ldo8_vol ldo8 voltage setting 0000:2.3v 0001:2.4v 0010:2.5v 0011:2.6v 0100:2.7v 0101:2.8v 0110:2.9v 0111:3.0v 1000:3.1v 1001:3.2v 1010:3.3v others 3.3v r/w 1000 10 1 reserved reserved r/w 0 0 ldo8_en ldo8 enbale bit 0 disable 1 enable r/w 0 11.4.37 pmu_ldo9_ctl pmu_ldo9_ctl register default 0x4000 offset = 0x26 bit(s) name description r/w reset 15 13 ldo9_vol ldo9 voltage setting 000:1.0v r/w 010 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 96 001:1.1v 010:1.2v 011:1.3v 100:1.4v 101:1.5v others: 1.5v 12 1 reserved reserved r/w 0 0 ldo9_en ldo9 enable bit 0 disable 1 enable r/w 0 11.4.38 pmu_ldo10_ctl pmu_ldo10_ctl register default 0x8000 offset = 0x27 bit(s) name description r/w reset 15 12 ldo10_vol ldo10 voltage setting 0000:2.3v 0001:2.4v 0010:2.5v 0011:2.6v 0100:2.7v 0101:2.8v 0110:2.9v 0111:3.0v 1000:3.1v 1001:3.2v 1010:3.3v others: 3.3v r/w 1000 11 1 reserved reserved r/w 0 0 ldo10_en ldo10 enable bit 0 disable 1 enable r/w 0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 97 11.4.39 pmu_ldo11_ctl pmu_ldo12_ctl register default 0xb000 offset = 0x28 bit(s) name description r/w reset 15 13 ldo11_vol ldo11 voltage setting 000:2.6v 001:2.7v 010:2.8v 011:2.9v 100:3.0v 101:3.1v 110:3.2v 111:3.3v r/w 101 12 svcc_low_en svcc low-power protection enable 0 disable 1 enable r/w 1 11 0 reserved reserved r/w 0 11.4.40 pmu_switch_ctl pmu_switch_ctl register default 0x0000 offset = 0x29 bit(s) name description r/w reset 15 switch1_en switch1_en 0 disable 1 enable r/w 0 14 switch2_en switch2_en 0 disable 1 enable when the bit is 1 switch2 opened,; when it is 0, it closed. r/w 0 13 switch2_mod switch2 mode selection 0 switch 1 ldo when the bit is 0 switch2 is used as switch; r/w 0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 98 when it is 1 it used as ldo 12 switch2_ldo_vol_sel switch2 used as ldo, voltage step serring 0 output is 1.0~2.0v 1 output is 2.3~3.3v r/w 0 11 8 switch2_ldo_vol switch2 used as ldo, the voltage setting 0000 1.0v 2.3v 0001 1.1v 2.4v 0010 1.2v 2.5v 0011 1.3v 2.6v 0100 1.4v 2.7v 0101 1.5v 2.8v 0110 1.6v 2.9v 0111 1.7v 3.0v 1000 1.75v 3.05v 1001 1.8v 3.1v 1010 1.85v 3.15v 1011 1.9v 3.2v 1100 1.95v 3.25v 1101 2.0v 3.3v others 2.0v 3.3v r/w 0000 7 6 reserved reserved r/w 0 5 switch1_mode switch1 mode selection 0 switch 1 ldo when bit is 0 switch1 is used as switch, when it is 1 it used as ldo r/w 0 4 3 switch1_ldo_vol switch1 used as ldo, the voltage setting 00 3.0v 01 3.1v 10 3.2v 11 3.3v r/w 00 2 reserved reserved r/w 0 1 switch1_discharge_en switch1 discharge enable control 0 disbale 1 enable bit1 and bit2 cannot be 1 at the same time bit1 and bit15 cannot be 1 at the same time. r/w 0 0 reserved reserved r/w 0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 99 11.4.41 pmu_ov_ctl0 pmu_ov_ctl0 register default 0x5555 offset = 0x2a bit(s) name description r/w reset 15 reserved reserved r/w 0 14 dcdc1_ov_set dcdc1 output overvoltage setting 0 10% dc1out 1 20% dc1out if detecting dc1out voltage is higher than its setting more than 1ms , and its corresponding enable bit is 1, it will send out dcdc1 overvoltage suspend. r/w 1 13 reserved reserved r/w 0 12 dcdc2_ov_set dcdc2 output overvoltage setting 0 10% dc2out 1 20% dc2out if detecting dc2out voltage is higher than its setting more than 1ms , and its corresponding enable bit is 1, it will send out dcdc2 overvoltage suspend. r/w 1 11 reserved reserved r/w 0 10 dcdc3_ov_set dcdc3 output overvoltage setting 0 10% dc3out 1 20% dc3out if detecting dc3out voltage is higher than its setting more than 1ms , and its corresponding enable bit is 1, it will send out dcdc3 overvoltage suspend. r/w 1 9-8 dcdc4_ov_set dcdc4 output overvoltage setting 00 5% dc4out 01 10% dc4out 10 15% dc4out 11 20% dc4out if detecting dc4out voltage is higher than its setting more than 1ms , r/w 01 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 100 and its corresponding enable bit is 1, it will send out dcdc4 overvoltage suspend. 7-6 ldo1_ov_set ldo1 output overvoltage setting 00 7% ldo1out 01 11% ldo1out 10 15% ldo1out 11 20% ldo1out if detecting ldo1out voltage is higher than its setting more than 1ms , and its corresponding enable bit is 1, it will send out ldo1 overvoltage suspend. r/w 01 5-4 ldo2_ov_set ldo2 output overvoltage setting 00 5% ldo2out 01 10% ldo2out 10 15% ldo2out 11 20% ldo2out if detecting ldo2out voltage is higher than its setting more than 1ms , and its corresponding enable bit is 1, it will send out ldo2 overvoltage suspend.. r/w 01 3-2 ldo3_ov_set ldo3 output overvoltage setting 00 5% ldo3out 01 10% ldo3out 10 15% ldo3out 11 20% ldo3out if detecting ldo3out voltage is higher than its setting more than 1ms , and its corresponding enable bit is 1, it will send out ldo3 overvoltage suspend.. r/w 01 1-0 ldo4_ov_set ldo4 output overvoltage setting 00 5% ldo4out 01 10% ldo4out 10 15% ldo4out 11 20% ldo4out if detecting ldo4out voltage is higher than its setting more than 1ms , r/w 01 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 101 and its corresponding enable bit is 1, it will send out ldo4 overvoltage suspend.. 11.4.42 pmu_ov_ctl1 pmu_ov_ctl1 register default 0x5550 offset = 0x2b bit(s) name description r/w reset 15-14 ldo5_ov_set ldo5 output overvoltage setting 00 5% ldo5out 01 10% ldo5out 10 15% ldo5out 11 20% ldo5out if detecting ldo5out voltage is higher than its setting more than1ms , and its corresponding enable bit is 1, it will send out ldo5 overvoltage suspend.. r/w 01 13-12 ldo6_ov_set ldo6 output overvoltage setting 00 5% ldo6out 01 10% ldo6out 10 15% ldo6out 11 20% ldo6out if detecting ldo6out voltage is higher than its setting more than 1ms , and its corresponding enable bit is 1, it will send out ldo6 overvoltage suspend. r/w 01 11-10 ldo7_ov_set ldo7 output overvoltage setting 00 5% ldo7out 01 10% ldo7out 10 15% ldo7out 11 20% ldo7out if detecting ldo7out voltage is higher than its setting more than 1ms , and its corresponding enable bit is 1, it will send out ldo7 r/w 01 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 102 overvoltage suspend. 9-8 ldo8_ov_set ldo8 output overvoltage setting 00 5% ldo8out 01 10% ldo8out 10 15% ldo8out 11 20% ldo8out if detecting ldo8out voltage is higher than its setting more than 1ms , and its corresponding enable bit is 1, it will send out ldo8 overvoltage suspend. r/w 01 7-6 ldo9_ov_set ldo9 output overvoltage setting 00 5% ldo9out 01 10% ldo9out 10 15% ldo9out 11 20% ldo9out if detecting ldo9out voltage is higher than its setting more than 1ms , and its corresponding enable bit is 1, it will send out ldo9 overvoltage suspend. r/w 01 5-4 ldo10_ov_set ldo10 output overvoltage setting 00 5% ldo10out 01 10% ldo10out 10 15% ldo10out 11 20% ldo10out if detecting ldo10out voltage is higher than its setting more than 1ms , and its corresponding enable bit is 1, it will send out ldo10 overvoltage suspend r/w 01 3-0 reserved reserved r/w 0 11.4.43 pmu_ov_status pmu_ov_status register default 0x0000 offset = 0x2c bit(s) name description r/w reset free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 103 15 dcdc1_ov_status dcdc1 output overvoltage state indication 0 not overvoltage is detected in dcdc1 1 vervoltage is detected in dcdc1 r 0 14 dcdc2_ov_status dcdc2 output overvoltage state indication 0 not overvoltage is detected in dcdc2 1 vervoltage is detected in dcdc2 r 0 13 dcdc3_ov_status dcdc3 output overvoltage state indication 0 not overvoltage is detected in dcdc3 1 vervoltage is detected in dcdc3 r 0 12 dcdc4_ov_status dcdc4 output overvoltage state indication 0 not overvoltage is detected in dcdc4 1 vervoltage is detected in dcdc4 r 0 11 ldo1_ov_status ldo1 output overvoltage state indication 0 not overvoltage is detected in ldo1 1 vervoltage is detected in ldo1 r 0 10 ldo2_ov_status ldo2 output overvoltage state indication 0 not overvoltage is detected in ldo2 1 vervoltage is detected in ldo2 r 0 9 ldo3_ov_status ldo3 output overvoltage state indication 0 not overvoltage is detected in ldo3 1 vervoltage is detected in ldo3 r 0 8 ldo4_ov_status ldo4 output overvoltage state indication 0 not overvoltage is detected in ldo4 1 vervoltage is detected in ldo4 r 0 7 ldo5_ov_status ldo5 output overvoltage state indication 0 not overvoltage is detected in ldo5 1 vervoltage is detected in ldo5 r 0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 104 6 ldo6_ov_status ldo6 output overvoltage state indication 0 not overvoltage is detected in ldo6 1 vervoltage is detected in ldo6 r 0 5 ldo7_ov_status ldo7 output overvoltage state indication 0 not overvoltage is detected in ldo7 1 vervoltage is detected in ldo7 r 0 4 ldo8_ov_status ldo8 output overvoltage state indication 0 not overvoltage is detected in ldo8 1 vervoltage is detected in ldo8 r 0 3 ldo9_ov_status ldo9 output overvoltage state indication 0 not overvoltage is detected in ldo9 1 vervoltage is detected in ldo9 r 0 2 ldo10_ov_status ldo10 output overvoltage state indication 0 not overvoltage is detected in ldo10 1 vervoltage is detected in ldo10 r 0 1 reserved reserved r/w 0 0 status_clear2 state indicates to clear bit write 1 to this bit, it will clear bit15 ~2 of this register, after that, this bit turns to 0 automatically r/w 0x0 11.4.44 pmu_ov_en pmu_ov_en register default 0xfffc offset = 0x2d bit(s) name description r/w reset 15 dcdc1_ov_en dcdc1 output overvoltage detect enable 0 disable 1 enable r/w 1 14 dcdc2_ov _en dcdc2 output overvoltage detect enable r/w 1 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 105 0 disable 1 enable 13 dcdc3_ov _en dcdc3 output overvoltage detect enable 0 disable 1 enable r/w 1 12 dcdc4_ov _en dcdc4 output overvoltage detect enable 0 disable 1 enable r/w 1 11 ldo1_ov _en ldo1 output overvoltage detect enable 0 disable 1 enable r/w 1 10 ldo2_ov _en ldo2 output overvoltage detect enable 0 disable 1 enable r/w 1 9 ldo3_ov _en ldo3 output overvoltage detect enable 0 disable 1 enable r/w 1 8 ldo4_ov _en ldo4 output overvoltage detect enable 0 disable 1 enable r/w 1 7 ldo5_ov _en ldo5 output overvoltage detect enable 0 disable 1 enable r/w 1 6 ldo6_ov_en ldo6 output overvoltage detect enable 0 disable 1 enable r/w 1 5 ldo7_ov _en ldo7 output overvoltage detect enable 0 disable 1 enable r/w 1 4 ldo8_ov _en ldo8 output overvoltage detect enable 0 disable 1 enable r/w 1 3 ldo9_ov _en ldo9 output overvoltage detect enable 0 disable 1 enable r/w 1 2 ldo10_ov _en ldo10 output overvoltage detect enable 0 disable r/w 1 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 106 1 enable 1:0 reserved reserved r/w 0 11.4.45 pmu_ov_int_en pmu_ov_int_en register default 0xfffc offset = 0x2e bit(s) name description r/w reset 15 dcdc1_ov_int_en dcdc1 output overvoltage detect enable 0 disable 1 enable r/w 1 14 dcdc2_ov_int _en dcdc2 output overvoltage detect enable 0 disable 1 enable r/w 1 13 dcdc3_ov_int _en dcdc3 output overvoltage detect enable 0 disable 1 enable r/w 1 12 dcdc4_ov_int _en dcdc4 output overvoltage detect enable 0 disable 1 enable r/w 1 11 ldo1_ov_int _en ldo1 output overvoltage detect enable 0 disable 1 enable r/w 1 10 ldo2_ov_int _en ldo2 output overvoltage detect enable 0 disable 1 enable r/w 1 9 ldo3_ov_int _en ldo3 output overvoltage detect enable 0 disable 1 enable r/w 1 8 ldo4_ov_int _en ldo4 output overvoltage detect enable 0 disable 1 enable r/w 1 7 ldo5_ov_int _en ldo5 output overvoltage detect enable 0 disable r/w 1 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 107 1 enable 6 ldo6_o_int v_en ldo6 output overvoltage detect enable 0 disable 1 enable r/w 1 5 ldo7_ov_int _en ldo7 output overvoltage detect enable 0 disable 1 enable r/w 1 4 ldo8_ov_int _en ldo8 output overvoltage detect enable 0 disable 1 enable r/w 1 3 ldo9_ov_int _en ldo9 output overvoltage detect enable 0 disable 1 enable r/w 1 2 ldo10_ov_int _en ldo10 output overvoltage detect enable 0 disable 1 enable r/w 1 1:0 reserved reserved r/w 0 11.4.46 pmu_oc_ctl pmu_ov_ctl register default 0x0000 offset = 0x2f bit(s) name description r/w reset 15 ldo1_oc_set ldo1 output overcurrent setting 0 800ma 1 900ma if ldo1 comes up ov ercurrent, then entering standby directly r/w 0 14 ldo2_oc_set ldo2 output overcurrent setting 0 400ma 1 500ma if ldo2 comes up ov ercurrent, then entering standby directly r/w 0 13 ldo3_oc_set ldo3 output overcurrent setting 0 500ma 1 600ma if ldo3 comes up ov ercurrent, then r/w 0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 108 entering standby directly 12 ldo4_oc_set ldo4 output overcurrent setting 0 800ma 1 900ma if detecting ldo4out output current is beyond its setting, and its corresponding suspend is enable, it will be interrupt, and close this ldo. to restart the ldo,must disable first and then enable again,or disable the overcurrent detect of the ldo. r/w 0 11 ldo5_oc_set ldo5 output overcurrent setting 0 300ma 1 400ma if detecting ldo5out output current is beyond its setting, and its corresponding suspend is enable, it will be interrupt, and close this ldo. to restart the ldo,must disable first and then enable again,or disable the overcurrent detect of the ldo r/w 0 10 ldo6_oc_set ldo6 output overcurrent setting 0 400ma 1 500ma if ldo6 come up overcurrent, then entering standby mode directly. r/w 0 9 ldo7_oc_set ldo7 output overcurrent setting 0 400ma 1 500ma if detecting ldo7out output current is beyond its setting, and its corresponding suspend is enable, it will be interrupt, and close this ldo. to restart the ldo,must disable first and then enable again,or disable the overcurrent detect of the ldo r/w 0 8 ldo8_oc_set ldo8 output overcurrent setting 0 300ma 1 400ma if detecting ldo8out output current r/w 0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 109 is beyond its setting, and its corresponding suspend is enable, it will be interrupt, and close this ldo. to restart the ldo,must disable first and then enable again,or disable the overcurrent detect of the ldo 7 ldo9_oc_set ldo9 output overcurrent setting 0 300ma 1 400ma if detecting ldo9out output current is beyond its setting, and its corresponding suspend is enable, it will be interrupt, and close this ldo. to restart the ldo,must disable first and then enable again,or disable the overcurrent detect of the ldo r/w 0 6 ldo10_oc_set ldo10 output overcurrent setting 0 300ma 1 400ma if detecting ldo10out output current is beyond its setting, and its corresponding suspend is enable, it will be interrupt, and close this ldo. to restart the ldo,must disable first and then enable again,or disable the overcurrent detect of the ldo r/w 0 5:0 reserved reserved r/w 0 11.4.47 pmu_oc_status pmu_oc_status register default 0x0000 offset = 0x30 bit(s) name description r/w reset 15 ldo1_oc_status ldo1 output overcurrent state indication 0 not overcurrentis detected in ldo1 1 overcurrent is detected in ldo1 after ldo overcurrent, hardware r 0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 110 shutoff this ldo, and set 1 to this bit. 14 ldo2_oc_status ldo2 output overcurrent state indication 0 not overcurrentis detected in ldo2 1 overcurrent is detected in ldo2 after ldo overcurrent, hardware shutoff this ldo, and set 1 to this bit. r 0 13 ldo3_oc_status ldo3 output overcurrent state indication 0 not overcurrentis detected in ldo3 1 overcurrent is detected in ldo3 after ldo overcurrent, hardware shutoff this ldo, and set 1 to this bit. r 0 12 ldo4_oc_status ldo4 output overcurrent state indication 0 not overcurrentis detected in ldo4 1 overcurrent is detected in ldo4 after ldo overcurrent, hardware shutoff this ldo, and set 1 to this bit. r 0 11 ldo5_oc_status ldo5 output overcurrent state indication 0 not overcurrentis detected in ldo5 1 overcurrent is detected in ldo5 after ldo overcurrent, hardware shutoff this ldo, and set 1 to this bit. r 0 10 ldo6_oc_status ldo6 output overcurrent state indication 0 not overcurrentis detected in ldo6 1 overcurrent is detected in ldo6 after ldo overcurrent, hardware shutoff this ldo, and set 1 to this bit. r 0 9 ldo7_oc_status ldo7 output overcurrent state indication 0 not overcurrentis detected in ldo7 1 overcurrent is detected in ldo7 after ldo overcurrent, hardware shutoff this ldo, and set 1 to this bit. r 0 8 ldo8_oc_status ldo8 output overcurrent state indication 0 not overcurrentis detected in ldo8 r 0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 111 1 overcurrent is detected in ldo8 after ldo overcurrent, hardware shutoff this ldo, and set 1 to this bit. 7 ldo9_oc_status ldo9 output overcurrent state indication 0 not overcurrentis detected in ldo9 1 overcurrent is detected in ldo9 after ldo overcurrent, hardware shutoff this ldo, and set 1 to this bit. r 0 6 ldo10_oc_status ldo10 output overcurrent state indication 0 not overcurrentis detected in ldo10 1 overcurrent is detected in ldo10 after ldo overcurrent, hardware shutoff this ldo, and set 1 to this bit. r 0 5:1 reserved reserved r/w 0 0 status_clear3 state indication clear bit write 1 to this bit, then clear bit15~2 of this register, after clearing, the bit turns to 0 r/w 0x0 11.4.48 pmu_oc_en pmu_oc_en register default 0xffc0 offset = 0x31 bit(s) name description r/w reset 15 ldo1_oc_en ldo1 output overcurrent detect enable 0 disable 1 enable r/w 1 14 ldo2_oc_en ldo2 output overcurrent detect enable 0 disable 1 enable r/w 1 13 ldo3_oc_en ldo3 output overcurrent detect enable 0 disable 1 enable r/w 1 12 ldo4_oc_en ldo4 output overcurrent detect enable 0 disable 1 enable r/w 1 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 112 11 ldo5_oc_en ldo5 output overcurrent detect enable 0 disable 1 enable r/w 1 10 ldo6_oc_en ldo6 output overcurrent detect enable 0 disable 1 enable r/w 1 9 ldo7_oc_en ldo7 output overcurrent detect enable 0 disable 1 enable r/w 1 8 ldo8_oc_en ldo8 output overcurrent detect enable 0 disable 1 enable r/w 1 7 ldo9_oc_en ldo9 output overcurrent detect enable 0 disable 1 enable r/w 1 6 ldo10_oc_en ldo10 output overcurrent detect enable 0 disable 1 enable r/w 1 5:0 reserved reserved r/w 0 11.4.49 pmu_oc_int_en pmu_oc_int_en register default 0x1bc0 offset = 0x32 bit(s) name description r/w reset 15 13 reserved reserved r/w 0 12 ldo4_oc_int _en ldo4 output overcurrent suspend enable 0 disable 1 enable r/w 1 11 ldo5_oc_int _en ldo5 output overcurrent suspend enable 0 disable 1 enable r/w 1 10 reserved reserved r/w 0 9 ldo7_oc_int _en ldo7 output overcurrent suspend enable r/w 1 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 113 0 disable 1 enable 8 ldo8_oc_int _en ldo8 output overcurrent suspend enable 0 disable 1 enable r/w 1 7 ldo9_oc_int _en ldo9 output overcurrent suspend enable 0 disable 1 enable r/w 1 6 ldo10_oc_int _en ldo9 output overcurrent suspend enable 0 disable 1 enable r/w 1 5:0 reserved reserved r/w 0 11.4.50 pmu_uv_ctl0 pmu_uv_ctl0 register default 0x5555 offset = 0x33 bit(s) name description r/w reset 15 reserved reserved r/w 0 14 dcdc1_uv_set dcdc1 output undervoltage setting 0 10% dc1out 1 20% dc1out if detecting dc1out voltage is lower than the settings more than 1ms , and its corresponding enable bit is 1 dcdc1 undervoltage suspend will be sent out. r/w 1 13 reserved reserved r/w 0 12 dcdc2_uv_set dcdc2 output undervoltage setting 0 10% dc2out 1 20% dc2out if detecting dc2out voltage is lower than the settings more than 1ms , and its corresponding enable bit is 1 dcdc2 undervoltage suspend r/w 1 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 114 will be sent out. 11 reserved reserved r/w 0 10 dcdc3_uv_set dcdc3 output undervoltage setting 0 10% dc3out 1 20% dc3out if detecting dc3out voltage is lower than the settings more than 1ms , and its corresponding enable bit is 1 dcdc3 undervoltage suspend will be sent out. r/w 1 9-8 dcdc4_uv_set dcdc4 output undervoltage setting 00 5% dc4out 01 10% dc4out 10 15% dc4out 11 20% dc4out if detecting dc4out voltage is lower than the settings more than 1ms , and its corresponding enable bit is 1 dcdc4 undervoltage suspend will be sent out. r/w 01 7-6 ldo1_uv_set ldo1 output undervoltage setting 00 5% ldo1out 01 10% ldo1out 10 15% ldo1out 11 20% ldo1out if detecting ldo1out voltage is lower than the settings more than 1ms , and its corresponding enable bit is 1 ldo1 undervoltage suspend will be sent out. r/w r/w 01 5-4 ldo2_uv_set ldo2 output undervoltage setting 00 5% ldo2out 01 10% ldo2out 10 15% ldo2out 11 20% ldo2out if detecting ldo2out voltage is lower than the settings more than 1ms , and its corresponding enable bit is 1 ldo2 undervoltage suspend will be sent out. r/w 01 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 115 3-2 ldo3_uv_set ldo3 output undervoltage setting 00 5% ldo3out 01 10% ldo3out 10 15% ldo3out 11 20% ldo3out if detecting ldo3out voltage is lower than the settings more than 1ms , and its corresponding enable bit is 1 ldo3 undervoltage suspend will be sent out. r/w 01 1-0 ldo4_uv_set ldo4 output undervoltage setting 00 5% ldo4out 01 10% ldo4out 10 15% ldo4out 11 20% ldo4out if detecting ldo4out voltage is lower than the settings more than 1ms , and its corresponding enable bit is 1 ldo4 undervoltage suspend will be sent out. r/w 01 11.4.51 pmu_uv_ctl1 pmu_uv_ctl1 register default 0x5550 offset = 0x34 bit(s) name description r/w reset 15-14 ldo5_uv_set ldo5 output undervoltage setting 00 5% ldo5out 01 10% ldo5out 10 15% ldo5out 11 20% ldo5out if detecting ldo5out voltage is lower than the settings more than 1ms , and its corresponding enable bit is 1 ldo5 undervoltage suspend will be sent out. r/w 01 13-12 ldo6_uv_set ldo6 output undervoltage setting 00 5% ldo6out r/w 01 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 116 01 10% ldo6out 10 15% ldo6out 11 20% ldo6out if detecting ldo6out voltage is lower than the settings more than 1ms , and its corresponding enable bit is 1 ldo6 undervoltage suspend will be sent out. 11-10 ldo7_uv_set ldo7 output undervoltage setting 00 5% ldo7out 01 10% ldo7out 10 15% ldo7out 11 20% ldo7out if detecting ldo7out voltage is lower than the settings more than 1ms , and its corresponding enable bit is 1 ldo7 undervoltage suspend will be sent out. r/w 01 9-8 ldo8_uv_set ldo8 output undervoltage setting 00 5% ldo8out 01 10% ldo8out 10 15% ldo8out 11 20% ldo8out if detecting ldo8out voltage is lower than the settings more than 1ms , and its corresponding enable bit is 1 ldo8 undervoltage suspend will be sent out. r/w 01 7-6 ldo9_uv_set ldo9 output undervoltage setting 00 5% ldo9out 01 10% ldo9out 10 15% ldo9out 11 20% ldo9out if detecting ldo9out voltage is lower than the settings more than 1ms , and its corresponding enable bit is 1 ldo9 undervoltage suspend will be sent out. r/w 01 5-4 ldo10_uv_set ldo10 output undervoltage setting 00 5% ldo10out r/w 01 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 117 01 10% ldo10out 10 15% ldo10out 11 20% ldo10out if detecting ldo10out voltage is lower than the settings more than 1ms , and its corresponding enable bit is 1 ldo10 undervoltage suspend will be sent out. 3-0 reserved reserved r/w 0 11.4.52 pmu_uv_status pmu_uv_status register default 0x0000 offset = 0x35 bit(s) name description r/w reset 15 dcdc1_uv_status dcdc1 output undervoltage state indication 0 not undervoltage detected in dcdc1 1 undervoltageis detected in dcdc1 r 0 14 dcdc2_uv_status dcdc2 output undervoltage state indication 0 not undervoltage detected in dcdc2 1 undervoltageis detected in dcdc2 r 0 13 dcdc3_uv_status dcdc3 output undervoltage state indication 0 not undervoltage detected in dcdc3 1 undervoltageis detected in dcdc3 r 0 12 dcdc4_uv_status dcdc4 output undervoltage state indication 0 not undervoltagedetected in dcdc4 1 undervoltageis detected in dcdc4 r 0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 118 11 ldo1_uv_status ldo1 output undervoltage state indication 0 not undervoltage detected in ldo1 1 undervoltageis detected in ldo1 r 0 10 ldo2_uv_status ldo2 output undervoltage state indication 0 not undervoltage detected in ldo2 1 undervoltageis detected in ldo2 r 0 9 ldo3_uv_status ldo3 output undervoltage state indication 0 not undervoltage detected in ldo3 1 undervoltageis detected in ldo3 r 0 8 ldo4_uv_status ldo4 output undervoltage state indication 0 not undervoltage detected in ldo4 1 undervoltageis detected in ldo4 r 0 7 ldo5_uv_status ldo5 output undervoltage state indication 0 not undervoltagedetected in ldo5 1 undervoltageis detected in ldo5 r 0 6 ldo6_uv_status ldo6 output undervoltage state indication 0 not undervoltage detected in ldo6 1 undervoltageis detected in ldo6 r 0 5 ldo7_uv_status ldo7 output undervoltage state indication 0 not undervoltage detected in ldo7 1 undervoltageis detected in ldo7 r 0 4 ldo8_uv_status ldo8 output undervoltage state indication 0 not undervoltage detected in ldo8 1 undervoltageis detected in ldo8 r 0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 119 3 ldo9_uv_status ldo9 output undervoltage state indication 0 not undervoltage detected in ldo9 1 undervoltageis detected in ldo9 r 0 2 ldo10_uv_status ldo10 output undervoltage state indication 0 not undervoltage detected in ldo10 1 undervoltageis detected in ldo10 r 0 1 reserved reserved r/w 0 0 status_clear4 state indication clear bit write 1 to this bit, then clear bit15~2 of this register, after clearing, the bit turns to 0 r/w 0x0 11.4.53 pmu_uv_en pmu_uv_en register default 0xfffc offset = 0x36 bit(s) name description r/w reset 15 dcdc1_uv_en dcdc1 output undervoltage detect enable 0 disable 1 enable r/w 1 14 dcdc2_uv_en dcdc2 output undervoltage detect enable 0 disable 1 enable r/w 1 13 dcdc3_uv_en dcdc3 output undervoltage detect enable 0 disable 1 enable r/w 1 12 dcdc4_uv_en dcdc4 output undervoltage detect enable 0 disable 1 enable r/w 1 11 ldo1_uv_en ldo1 output undervoltage detect r/w 1 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 120 enable 0 disable 1 enable 10 ldo2_uv_en ldo2 output undervoltage detect enable 0 disable 1 enable r/w 1 9 ldo3_uv_en ldo3 output undervoltage detect enable 0 disable 1 enable r/w 1 8 ldo4_uv_en ldo4 output undervoltage detect enable 0 disable 1 enable r/w 1 7 ldo5_uv_en ldo5 output undervoltage detect enable 0 disable 1 enable r/w 1 6 ldo6_uv_en ldo6 output undervoltage detect enable 0 disable 1 enable r/w 1 5 ldo7_uv_en ldo7 output undervoltage detect enable 0 disable 1 enable r/w 1 4 ldo8_uv_en ldo8 output undervoltage detect enable 0 disable 1 enable r/w 1 3 ldo9_uv_en ldo9 output undervoltage detect enable 0 disable 1 enable r/w 1 2 ldo10_uv_en ldo10 output undervoltage detect enable 0 disable 1 enable r/w 1 1-0 reserved reserved r/w 0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 121 11.4.54 pmu_uv_int_en pmu_uv_int_en register default 0xfffc offset = 0x37 bit(s) name description r/w reset 15 dcdc1_uv_en dcdc1 output undervoltage suspend enable 0 disable 1 enable r/w 1 14 dcdc2_uv_en dcdc2 output undervoltage suspend enable 0 disable 1 enable r/w 1 13 dcdc3_uv_en dcdc3 output undervoltage suspend enable 0 disable 1 enable r/w 1 12 dcdc4_uv_en dcdc4 output undervoltage suspend enable 0 disable 1 enable r/w 1 11 ldo1_uv_en ldo1 output undervoltage suspend enable 0 disable 1 enable r/w 1 10 ldo2_uv_en ldo2 output undervoltage suspend enable 0 disable 1 enable r/w 1 9 ldo3_uv_en ldo3 output undervoltage suspend enable 0 disable 1 enable r/w 1 8 ldo4_uv_en ldo4 output undervoltage suspend enable 0 disable 1 enable r/w 1 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 122 7 ldo5_uv_en ldo5 output undervoltage suspend enable 0 disable 1 enable r/w 1 6 ldo6_uv_en ldo6 output undervoltage suspend enable 0 disable 1 enable r/w 1 5 ldo7_uv_en ldo7 output undervoltage suspend enable 0 disable 1 enable r/w 1 4 ldo8_uv_en ldo8 output undervoltage suspend enable 0 disable 1 enable r/w 1 3 ldo9_uv_en ldo9 output undervoltage suspend enable 0 disable 1 enable r/w 1 2 ldo10_uv_en ldo10output undervoltage suspend enable 0 disable 1 enable r/w 1 1-0 reserved reserved r/w 0 11.4.55 pmu_ot_ctl pmu_ot_ctl register default 0x3b00 offset = 0x38 bit(s) name description r/w reset 15 ot_status ic overtemperature stae indication 0 not overtempreture detected 1 overtempreture detected write 1 clear 0 r/w 0 14:13 ot_set ic overtemperature suspend temperature setting 00 100 r/w 01 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 123 01 120 10 130 11 140 12 ot_int_en icovertemperature suspend enable 0 disable 1 enable r/w 1 11 ot_shutoff_en ic overtemperature shutoff enable 0 disable 1 enable r/w 1 10:9 ot_shutoff_set ic overtemperature shutoff temperature setting 00 110 01 130 10 150 11 160 r/w 01 8 ot_en ic overtemperature detect enable 0 disable 1 enable r/w 1 7-0 reserved reserved r/w 0 11.4.56 pmu_charger_ctl0 pmu_charger_ctl0 register default 0x325b offset = 0x39 bit(s) name description r/w reset 15 ench enable charge circuit 1: enable charge circuit 0: disable charge circuit. r/w 0 14 10 reserved reserved r/w 01100 9 trickleen enable trickle charge 0: disable 1: enable if this bit is 0,there is no pre-charging phase, and battery charging goes to constant current directly. r/w 1 8 0 reserved reserved r/w 001011011 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 124 11.4.57 pmu_charger_ctl1 pmu_charger_ctl1 register default 0x0040 offset = 0x3a bit(s) name description r/w reset 15 chgend charging end status. 0: not charging over 1: charging over. if battery is not full, this bit is 0; if battery is full, this bit is 1. r x 14 8 reserved reserved r x 7 4 reserved reserved r/w 0100 3:0 ichg_reg_cc charge constant current charge current configure 0000:50ma 0001:100ma 0010:200ma 0011:300ma 0100:400ma 0101:500ma 0110:600ma 0111:700ma 1000:800ma 1001:900ma 1010:1000ma 1011:1100ma 1100:1200ma 1101:1300ma 1110:1400ma 1111:1500ma r/w 0000 11.4.58 pmu_charger_ctl2 pmu_charger_ctl1 register default 0x0000 offset = 0x3b bit(s) name description r/w reset 15 6 reserved reserved r/w 0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 125 5 4 ichg_reg_t charge trickle charge current configure 00:50ma 01:100ma 10:200ma 11:300ma r/w 00 3 0 reserved reserved r/w 00 11.4.59 pmu_bakcharger_ctl pmu_bakcharger_ctl0 register default 0x2000 offset = 0x3c bit(s) name description r/w reset 15 bk_chgend charging end status. 0: not charging over 1: charging over. if battery is not full, this bit is 0; if battery is full, this bit is 1. r x 14:12 bk_chgis bak charger current set 000 1ma 001 5ma 010 10ma 011 25ma 100 50ma others reserved r/w 010 11 bk_vol bak charger stopv 0: 4.2v 1: 3v r/w 0 10 bk_chg_en bak charger enbale 0: disable 1: enable r/w 0 9:0 reserved reserved r/w 0 11.4.60 pmu_apds_ctl pmu_apds_ctl0 register default 0x15f8 offset = 0x3d free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 126 bit(s) name description r/w reset 15 vbus_control_en vbus voltage current control 0 enable 1 disable after enable this bit the system will be adjust current which is extract from vbus automatically,. in basis of the setting of bit14 to ensure vbus voltage is over the bit[11:10] threshold or make sure the extracted current from vbus lower than bit[13:12] setting. disable means to ensure the system?s power current prior. if enable this bit, bit8 is invalid. r/w 0 14 vbus_control_sel vbus control mode selection 0 voltage-limiting 1 current-limiting r/w 0 13:12 vbus_cur_ limited vbus current-limiting threshold current 00 100ma 01 300ma 10 500ma 11 800ma r/w 01 11:10 vbus_vol_ limited vbus voltage-limiting threshold voltage 00 4.2v 01 4.3v 10 4.4v 11 4.5v r/w 01 9 vbus_otg usb as otg vbus supply power for the drive, when it does this, it needs to write 1 to vbus_otg to avoid vbus supplying power to syspwr. 0 don?t close id from vbus to syspwr 1 close id from vbus to syspwr cut off vbus and syspwr r/w 0 8 vbus_fst_on when syspwr lower than setting,if vbus voltage is enough, open vbus rapidly. r/w 1 7 vbus_fst_off when syspwr higher than setting, it will shut off vbus rapidly. r/w 1 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 127 6 wall_fst_on when syspwr lower than setting,if wall voltage is enough, open wall rapidly. r/w 1 5 wall_fst_off when syspwr higher than setting, it will shut off wall rapidly. r/w 1 4 bat_fst_on when syspwr lower than setting,if bat voltage is enough, open bat rapidly. r/w 1 3 bat_fst_off when syspwr higher than setting, it will shut off wall rapidly. r/w 1 2 vbus_pd vbus 5k pull-down resistance enable r/w 0 1 wall_pd wall 5k pull-down resistance enable r/w 0 0 reserved reserved r/w 0 11.4.61 auxadc_ctl0 auxadc_ctl0 register default 0xffff offset = 0x3e bit(s) name description r/w reset 15 auxadc0_en auxadc0 adc enable 0: disable 1: enable r/w 1 14 auxadc1_en auxadc1 adc enable 0: disable 1: enable r/w 1 13 auxadc2_en auxadc2 adc enable 0: disable 1: enable r/w 1 12 auxadc3_en auxadc3 adc enable 0: disable 1: enable r/w 1 11 vbusvadc_en vbus volatge adc enable 0: disable 1: enable r/w 1 10 wallvadc_en wall volatge adc enable 0: disable 1: enable r/w 1 9 syspwradc_en syspwr volatge adc enable r/w 1 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 128 0: disable 1: enable 8 bakbatadc_en bakbat voltage adc enable 0: disable 1: enable r/w 1 7 batvadc_en bat volatge adc enable 0: disable 1: enable r/w 1 6 temp_adc temp adc enable 0: disable 1: enable r/w 1 5 remcon_adc_en remcon adc enable 0: disable 1: enable r/w 1 4 batiadc_en bat current adc enable 0: disable 1: enable r/w 1 3 walliadc_en wall current adc enable 0: disable 1: enable r/w 1 2 vbusiadc_en vbus current adc enable 0: disable 1: enable r/w 1 1 chgiadc_en charger current adc enable 0: disable 1: enable r/w 1 0 irefadc_en/ svcc_adc_en current ref adc enable/ svcc adc enable 0: disable 1: enable r/w 1 11.4.62 auxadc_ctl1 auxadc_ctl1 register default 0x000b offset = 0x3f bit(s) name description r/w reset 15-4 reserved reserved r/w 0x0 3 adc_comp_tmen adc comp offset trimming r/w 1 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 129 0 : disable 1 : enable 2 adc_comp_bias adc comp bias 0: 4ua 1: 6ua r/w 0 1 adc_input_range adc input range 0: 0~1.5v 1: 0~3.0v r/w 1 0 adc_clock_adj adc clock adjust 0: 300k 1: 400k r/w 1 11.4.63 pmu_batvadc pmu_batadc register default 0x0000 offset = 0x40 bit(s) name description r/w reset 15-10 reserved reserved r 0 9 0 batvadc batvadc data r x 11.4.64 pmu_batiadc pmu_batiadc register default 0x0000 offset = 0x41 bit(s) name description r/w reset 15-10 reserved reserved r 0 9 0 batiadc batiadc data r x 11.4.65 pmu_wallvadc pmu_walladc register default 0x0000 offset = 0x42 bit(s) name description r/w reset 15-10 reserved reserved r 0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 130 9 0 wallvadc wallvadc data r x 11.4.66 pmu_walliadc pmu_walliadc register default 0x0000 offset = 0x43 bit(s) name description r/w reset 15-10 reserved reserved r 0 9 0 walliadc walliadc data r x 11.4.67 pmu_vbusvadc pmu_vbusadc register default 0x0000 offset = 0x44 bit(s) name description r/w reset 15-10 reserved reserved r 0 9 0 vbusvadc vbusvadc data r x 11.4.68 pmu_vbusiadc pmu_vbusiadc register default 0x0000 offset = 0x45 bit(s) name description r/w reset 15-10 reserved reserved r 0 9 0 vbusiadc vbusiadc data r x 11.4.69 pmu_syspwradc pmu_syspwradc register default 0x0000 offset = 0x46 bit(s) name description r/w reset 15-10 reserved reserved r 0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 131 9 0 syspwradc syspwradc data r x 11.4.70 pmu_remconadc pmu_remconadc register default 0x0000 offset = 0x47 bit(s) name description r/w reset 15-10 reserved reserved r 0 9 0 remconadc remcon adc data r x 11.4.71 pmu_svccadc pmu_svccadc register default 0x0000 offset = 0x48 bit(s) name description r/w reset 15-10 reserved reserved r 0 9 0 svccadc svcc adc data r x 11.4.72 pmu_chgiadc pmu_ chgiadc register default 0x0000 offset = 0x49 bit(s) name description r/w reset 15-10 reserved reserved r 0 9 0 chgiadc chgiadc data r x 11.4.73 pmu_irefadc pmu_ irefadc register default 0x0000 offset = 0x4a bit(s) name description r/w reset free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 132 15-10 reserved reserved r 0 9 0 irefadc irefadc data r x 11.4.74 pmu_bakbatadc pmu_ bakbatadc register default 0x0000 offset = 0x4b bit(s) name description r/w reset 15-10 reserved reserved r 0 9 0 bakbatadc bak battery voltage adc data r x 11.4.75 pmu_ictempadc pmu_ ictempadcregister default 0x0000 offset = 0x4c bit(s) name description r/w reset 15-10 reserved reserved r 0 9 0 ictempadc ictempadc adc data r x free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 133 12. auxiliaty adc 12.1 module description atc260x contains 10-bit, 16-channel analog-to-digital converters (adcs) the purpose of each adc distributes as follows: adc_0 adc_1 adc_2 adc_3 adc_4 adc_5 adc_6 adc_7 batv bati vbusv vbusi syspwrv wallv walli ichg adc_8 adc_9 adc_10 adc_11 adc_12 adc_13 adc_14 adc_15 svcc/ iref rem_ con ictemp bakba t auxadc 0 auxadc 1 auxadc2 auxad c3 wa l l syspwr vbus will divided by 2.5 before sent to adc so the relation between voltage value of wall syspwr vbus and their adc value is: 5 . 2 * * lsb data v = while bat will divided by 2 before sent to adc, so the relation of bat and its adc is : 2 * * lsb data v = in addition, adc also needs to detect the cu rrent from vbus to syspwr, from bat to syspwr, charger?s charging current, bake bat voltage, svcc voltage, battery tempreture and etc. among these, full scale range of bati adc and walli adc vbusi adc ichg is 1500ma so the relation of their adc data?s corresponding current data is: ) ( 1024 / 1500 * * ma data lsbi data i = = ictemp?s adc data and tempreture relationship is as follows: ) ( 899 . 14 * 1949 . 0 c data temp o ? = for remcon adc its input range is 0-3v while drive-by-wire adc is distinguished by button?s different voltage. when the wire button?s power voltage is changed, the corresponding voltage of same button is different, so remcon adc data reflects the ratio of remcon voltage and svcc voltage: svcc data mconadc mcon * ) 1024 / _ (re re = among these remconadc_data/1024 could react different button?s value, it shows the button?s value is remconadc_data/1024 times of svcc auxadc0~3 is external general used adc free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 134 12.2 register list auxadc block address name base address auxadc 0x0000 table 0-1 auxadc controller registers offset register name description 0x3e auxadc_ctl0 pmu auxadc control register0 0x3f auxadc_ctl1 pmu auxadc control register1 0x40 pmu_batvadc pmu batvadc register 0x41 pmu_batiadc pmu batiadc register 0x42 pmu_wallvadc pmu wallvadc register 0x43 pmu_walliadc pmu walliadc register 0x44 pmu_vbusvadc pmu vbusvadc register 0x45 pmu_vbusiadc pmu vbusiadc register 0x46 pmu_syspwradc pmu syspwradc register 0x47 pmu_remconadc pmu remconadc register 0x48 pmu_svccadc pmu svccadc register 0x49 pmu_chgiadc pmu chgiadc register 0x4a pmu_irefadc pmu irefadc register 0x4b pmu_bakbatadc pm u bakbatadc register 0x4c pmu_ictempadc pmu ictempadc register 0x4d auxadc0 pmu auxadc0 register 0x4e auxadc1 pmu auxadc1 register 0x4f auxadc2 pmu auxadc2 register 0x50 auxadc3 pmu auxadc3 register 12.2.1 auxadc_ctl0 auxadc_ctl0 register default 0xffff offset = 0x3e bit(s) name description r/w reset 15 auxadc0_en auxadc0 adc enable 0: disable r/w 1 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 135 1: enable 14 auxadc1_en auxadc1 adc enable 0: disable 1: enable r/w 1 13 auxadc2_en auxadc2 adc enable 0: disable 1: enable r/w 1 12 auxadc3_en auxadc3 adc enable 0: disable 1: enable r/w 1 11 vbusvadc_en vbus volatge adc enable 0: disable 1: enable r/w 1 10 wallvadc_en wall volatge adc enable 0: disable 1: enable r/w 1 9 syspwradc_en syspwr volatge adc enable 0: disable 1: enable r/w 1 8 bakbatadc_en bakbat voltage adc enable 0: disable 1: enable r/w 1 7 batvadc_en bat volatge adc enable 0: disable 1: enable r/w 1 6 temp_adc temp adc enable 0: disable 1: enable r/w 1 5 remcon_adc_en remcon adc enable 0: disable 1: enable r/w 1 4 batiadc_en bat current adc enable 0: disable 1: enable r/w 1 3 walliadc_en wall current adc enable 0: disable 1: enable r/w 1 2 vbusiadc_en vbus current adc enable 0: disable 1: enable r/w 1 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 136 1 chgiadc_en charger current adc enable 0: disable 1: enable r/w 1 0 irefadc_en/ svcc_adc_en current ref adc enable/ svcc adc enable 0: disable 1: enable r/w 1 12.2.2auxadc_ctl1 auxadc_ctl1 register default 0x000b offset = 0x3f bit(s) name description r/w reset 15-4 reserved reserved r/w 0x0 3 adc_comp_tmen adc comp offset trimming 0 : disable 1 : enable r/w 1 2 adc_comp_bias adc comp bias 0: 4ua 1: 6ua r/w 0 1 adc_input_range adc input range 0: 0~1.5v 1: 0~3.0v r/w 1 0 adc_clock_adj adc clock adjust 0: 300k 1: 400k r/w 1 12.2.3 auxadc_batv batadc register default 0x0000 offset = 0x40 bit(s) name description r/w reset 15-10 reserved reserved r 0 9 0 batvadc batvadc data r x free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 137 12.2.4 auxadc_bati batiadc register default 0x0000 offset = 0x41 bit(s) name description r/w reset 15-10 reserved reserved r 0 9 0 batiadc batiadc data r x 12.2.5 auxadc_wallv walladc register default 0x0000 offset = 0x42 bit(s) name description r/w reset 15-10 reserved reserved r 0 9 0 wallvadc wallvadc data r x 12.2.6 auxadc__walli walliadc register default 0x0000 offset = 0x43 bit(s) name description r/w reset 15-10 reserved reserved r 0 9 0 walliadc walliadc data r x 12.2.7 auxadc__vbusv vbusadc register default 0x0000 offset = 0x44 bit(s) name description r/w reset 15-10 reserved reserved r 0 9 0 vbusvadc vbusvadc data r x free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 138 12.2.8 auxadc_vbusi vbusiadc register default 0x0000 offset = 0x45 bit(s) name description r/w reset 15-10 reserved reserved r 0 9 0 vbusiadc vbusiadc data r x 12.2.9 auxadc_syspwr syspwradc register default 0x0000 offset = 0x46 bit(s) name description r/w reset 15-10 reserved reserved r 0 9 0 syspwradc syspwradc data r x 12.2.10 auxadc_remcon remconadc register default 0x0000 offset = 0x47 bit(s) name description r/w reset 15-10 reserved reserved r 0 9 0 remconadc remcon adc data r x 12.2.11 auxadc_svcc svccadc register default 0x0000 offset = 0x48 bit(s) name description r/w reset 15-10 reserved reserved r 0 9 0 svccadc svcc adc data r x free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 139 12.2.12 auxadc_chgi chgiadc register default 0x0000 offset = 0x49 bit(s) name description r/w reset 15-10 reserved reserved r 0 9 0 chgiadc chgiadc data r x 12.2.13 auxadc_iref irefadc register default 0x0000 offset = 0x4a bit(s) name description r/w reset 15-10 reserved reserved r 0 9 0 irefadc irefadc data r x 12.2.14 auxadc_bakbat bakbatadc register default 0x0000 offset = 0x4b bit(s) name description r/w reset 15-10 reserved reserved r 0 9 0 bakbatadc bak battery voltage adc data r x 12.2.15 auxadc_ictemp ictempadcregister default 0x0000 offset = 0x4c bit(s) name description r/w reset 15-10 reserved reserved r 0 9 0 ictempadc ictempadc adc data r x free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 140 12.2.16 auxadc0 auxadc0 register default 0x0000 offset = 0x4d bit(s) name description r/w reset 15-10 reserved reserved r 0 9 0 auxadc0 auxadc0 data r x 12.2.17 auxadc1 pmu_ auxadc1 register default 0x0000 offset = 0x4e bit(s) name description r/w reset 15-10 reserved reserved r 0 9 0 auxadc1 auxadc1 data r x 12.2.18 auxadc2 pmu_ auxadc2 register default 0x0000 offset = 0x4f bit(s) name description r/w reset 15-10 reserved reserved r 0 9 0 auxadc2 auxadc2 data r x 12.2.19 auxadc3 pmu_ auxadc3 register default 0x0000 offset = 0x50 bit(s) name description r/w reset 15-10 reserved reserved r 0 9 0 auxadc3 auxadc3 data r x free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 141 13. real-time clock 13.1 module description rtc module is used in timing and alarm clock etc function, it supports power off alarm clock and timing power on. figure 0-1 external losc detects working circuit?s sequence: if it detects that losc has oscillationwave, then detecting circuit 1 will delay about 1ms to configure register rtc_ctl[3] as 1. if detecting the external losc has no oscillationwave, then detecting circuit 1 will delay about 3ms to configure register rtc_ctl[3] as 0. detecting circuit 2 ha s the same function with this, if the system use losc_clk and there is no clock, then rtcvdd_ok ?s signal will be pulled down, and the whole system reseted. when the system power on and enter to standby, its inner/outer losc manage process is(red arrow is losc?s external normal flow ): free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 142 losc losc enable run brom rtc_ctl[3]=1 ? losc rtc_ctl[5]=1 losc rtc_ctl[5]=0 losc / losc standby rtc_ctl[3]=1 ? losc standby rtc_ctl[5]=1 ??? losc rtc_ctl[5]=0 losc / losc standby / losc figure 0-2 the handle of external losc oscillation stop: no matter the system is standby or in normal running mode, only if system chooses the external losc and the external is stop oscillation, detecting circuit 2 will pull down rtcvdd_ok signal, th e whole system reset. then y ou power on, system default use internal losc, it can run well as the above flow. calendar when rtce =1, rtc_h rtc_ms and rtc_ymd count up with losc_clk. cpu can read the two registers at any time for getting the real time, but can not write the two registers. when rtce =0, the two registers can be written to set the real time. alarm when rtce=alie=1,if rtc_halm=rtc_h rtc_msalm=rtc_ms and rtc_ymdalm=rtc_ymd , alarm irq will generate,it can be cleared by writing 1 to the bit alip. free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 143 13.2 register list rtc block address name base address rtc 0x0000 table 0-1 rtc controller registers offset register name description 0x52 rtc_ctl rtc control register 0x53 rtc_msalm rtc alarm minute second regiser 0x54 rtc_halm rtc alarm hour regiser 0x55 rtc_ymdalm rtc alarm year month date regiser 0x56 rtc_ms rtc minute second regiser 0x57 rtc_h rtc hour regiser 0x58 rtc_dc rtc day century regiser 0x59 rtc_ymd rtc year month date regiser 13.2.1 rtc_ctl calendar control register default 0x5a50 offset=0x052 bits name description access reset 15:14 lgs low frequency crystal oscillator gmnin select bits 00 01 10 11 r/w 01 13 12 losc_cp losc capacitor select 00 12pf 01 15pf 10 18pf 11 21pf r/w 01 11 rst rtc reset 1: normal 0: reset r/w 1 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 144 10 veri rtc verify clock enable switch rtc clock to 32k 1: enable 0: disable r/w 0 9 leap rtc leap year bit 1: leap year 0: not leap year r 1 8:7 test in test mode, select 4 test clock out to rtc test pad 0 2hz 1 8hz 2 128hz 3 32khz r/w 0 6 eosc external crystal osc enable 1: enable 0: disable r/w 1 5 ckss0 rtc_32k clock source select 1: external crystal osc 0: build-in osc r/w 0 4 rtce rtc enable 1: enable 0: disable r/w 1 3 ext_losc_state external losc state 0 external losc stop oscillating 1 external losc is oscillating r x 2 - reserved r 0 1 alie alarm irq enable 1: enable 0: dsiable r/w 0 0 alip alarm irq pending bit, writing 1 to this bit will clear it r/w 0 note 1 bit5: only when rtcvdd power off t horough, ckss0 will be reseted. 2 calendar and alarm mode need accurate low frequency clk, so choose the accurate external crystal osc in application. 3 losc_cp[15:14] the match capacitance of losc circuit choosing. it all depends on external 32.768khz crystal load capacitance, th e default step is usually 01 or 10. 4 lgs[13:12] the drive capacity strength of losc ci rcuit, the sequence of drive ability is 2b11>2b10>2b01>2b00 default is recommend used. 5 test[8:7] debug back door of losc. 6 ckss0[5] external losc and ic internal losc choose to change bit. 7 ext_losc_state[3] external losc oscillation state bit. free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 145 13.2.2 rtc_msalm calendar msalm register default 0x0000 offset=0x053 bits name description access reset 15:12 - reserved r 0 11:6 minal alarm minute setting 00h ? 3bh r/w 0 5:0 secal alarm second setting 00h ? 3bh r/w 0 13.2.3 rtc_halm calendar halm register default 0x0000 offset=0x054 bits name description access reset 15:5 - reserved r 0 4:0 houeal alarm hour setting 00h ? 17h r/w 0 13.2.4 rtc _ymdalm calendar ymdalm register default 0x0000 offset=0x055 bits name description access reset 15:9 yearal alarm year setting 00h ? 63h r/w 0 8:5 monal alarm month setting 01h ? 0ch r/w 0 4:0 dateal alarm day setting 01h ? 1fh r/w 0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 146 13.2.5 rtc_ms calendar ms register default 0x0000 offset=0x056 bits name description access reset 15:12 - reserved r 0 11:6 min time minute setting 00h ? 3bh r/w 0 5:0 sec time second setting 00h ? 3bh r/w 0 13.2.6 rtc_h calendar hour register default 0x0000 offset=0x057 bits name description access reset 15:5 - reserved r 0 4:0 hour time hour setting 00h ? 17h r/w 0 13.2.7 rtc_dc calendar dc register default 0x0080 offset=0x058 bits name description access reset 15:10 - reserved r 0 9:7 day time day setting 01h ? 07h r/w 001 6:0 cent time setting 00h ? 63h r/w 0 13.2.8 rtc_ymd calendar ymd register default 0x0021 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 147 offset=0x059 bits name description access reset 15:9 year time year setting 00h ? 63h r/w 0 8:5 mon time month setting 01h ? 0ch r/w 0001 4:0 date time day setting 01h ? 1fh r/w 00001 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 148 14. infrared remote controller 14.1 features support rc5\9012\nec(8bit)\air protocol, compatible 36khz, 38khz, 40khz carrier. support irc wake up need to connect an ir receiver when use. irc module would generate the wake up signal to pmu only when the received key data equal to the irc_wk register ?s data include nec 9012 rc5 and air mode. support rc5\9012\nec(8bit)\air protocol, compatible 36khz, 38khz, 40khz carrier. support irc wake up need to connect an ir receiver when use. irc module would generate the wake up signal to pmu only when the received key data equal to the irc_wk register ?s data include nec 9012 rc5 and air mode. 14.2features module description 9012 protocol the 9012 protocol uses a pulse distance encoding of the bits. each pulse is one tm (560s) long 38khz carrier burst. a logical "1" takes 4tm (2.25ms) to transmit, while a logical "0" is only 2tm (1.12ms). the recommended carrier duty-cycle is 1/4 or 1/3. tm=256/fosc=0.56ms (fosc=455khz) repetition time=192tm=108ms carrier frequency = fosc/12 8 bit customer code and 8 bit command code length customer and command are transmitted twice for reliability pulse distance modulation bit time of 2tm(1.12ms) for logic ?0? or 4tm (2.25ms) for logic ?1? with this protocol the lsb is transmitted first. in this case customer code and command is transmitted. a message is started by 8tm (4.5ms) agc burst, which was used to set the gain of the earlier ir receivers. this agc burst is then follow ed by 8tm (4.5ms) space, which is then followed by the customer code and command. customer code and command are transmitted twice. the second free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 149 time the command bits are inverted and can be used for verification of the received message. 4.5ms 4.5ms 8 bit customer code 8 bit customer code 8 bit command code 8 bit command anti-code lsb msb lsb msb 8tm 8tm figure 0-1 figure 0-2 a command is transmitted only once, even when the key on the remote control remains pressed. every 192tm a repeat code is transmitted for as long as the key remains down. this repeat code is simply one 8tm (4.5ms) agc pulse followed by one 8tm (4.5ms) space and a logic ?1? +1tm (560s) burst. figure 0-3 nec protocol(8bit) the nec protocol uses a pulse distance encoding of the bits. each pulse is one tm (560s) long 38khz carrier burst. a logical "1" takes 4tm (2.25ms) to transmit, while a logical "0" is only 2tm (1.12ms). the recommended carrier duty-cycle is 1/4 or 1/3. tm=256/fosc=0.56ms (fosc=455khz) repetition time=192tm=108ms carrier frequency = fosc/12 8 bit customer and 8 bit command length free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 150 customer and command are transmitted twice for reliability pulse distance modulation bit time of 2tm(1.12ms) for logic ?0? or 4tm (2.25ms) for logic ?1? with this protocol the lsb is transmitted first. in this case customer code and command is transmitted. a message is started by 16tm (9ms) agc burst, which was used to set the gain of the earlier ir receivers. this agc burst is then follow ed by 8tm (4.5ms) space, which is then followed by the customer code and command. customer code and command are transmitted twice. the second time all bits are inverted and can be used fo r verification of the received message. the total transmission time is constant because every bit is repeated with its inverted length. figure 0-4 figure 0-5 a command is transmitted only once, even when the key on the remote control remains pressed. every 192tm a repeat code is transmitted for as long as the key remains down. this repeat code is simply a 16tm (9ms) agc pulse followed by a 4tm (2.25ms) space and one tm (560s) burst. figure 0-6 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 151 16tm 4tm 1tm repeat code figure 0-7 rc5 protocol the protocol uses bi-phase modulation (or so-called manchester coding) of a 38khz ir carrier frequency. all bits are of equal length of 1.8ms in th is protocol, with half of the bit time filled with a burst of the 38khz carrier and the other half being idle. a logical zero is represented by a burst in the first half of the bit time. a logical one is represente d by a burst in the second half of the bit time. the pulse/pause ratio of the 38khz carrier frequency is 1/3 or 1/4, to reduce power consumption. 1 bit-time = 3 x 256 /fosc= 1.688ms (fosc=455khz) tm= 1 bit-time/2=0.844ms repetition time= 4 x 16 x 2tm=108ms carrier frequency = fosc/12 figure 0-8 figure 0-9 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 152 the first two pulses are the start pulses, and are both logical "1". please note that half a bit time is elapsed before the receiver will notice the real start of the message. the 3d bit is a toggle bit. this bit is inverted every time a key is released and pressed again. this way the receiver can distinguish between a key that remains down, or is pressed repeatedly. the next 5 bits represent the ir device address, which is sent with msb first. the address is followed by a 6 bit command, again sent with msb first. a message consists of a total of 14 bits, which adds up to a total duration of 28tm. sometimes a message may appear to be shorter because the first half of the start bit s1 remains idle. and if the last bit of the message is a logic "0" the last half bit of the message is idle too. as long as a key remains down the message will be repeated every 128tm(108ms). the toggle bit will retain the same logical level during all of these repeated messages. it is up to the receiver software to interpret this auto repeat feature. figure 0-10 air protocol the air protocol uses a pulse distance encoding of the bits. the recommende d carrier duty-cycle is 1/3. logic bit figure 0-11 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 153 tb = 190us 6 d t ; t0 = tb = 190us t1 = 360us; start symbol figure 0-12 ts = 500us, start symbol: ts+2*ts+tb =1690us frame: one start symbol and 18-bit data compose the frame. addr, t0, key 0, t1, key 1 chksum compose the 18-bit data. start addr [2:0] t0 key0 [4:0] t1 key1 [4:0] chksum [2:0] msb lsb msb lsb lsb lsb msb msb figure 0-13 name attribute purpose start 1 start symbol detect frame agc clock synchronize addr 3 normal bit customer code t0 1 normal bit toggle bit 0 key 0 5 normal bit key index 0 t1 1 normal bit toggle bit 1 key 1 5 normal bit key index 1 chksum 3 normal bit check bit notes except the start is start symbol the other all is normal data bit key 0/key 1 each support 31 keys, and the data b?00000 indicate that no key pressed down. free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 154 toggle bit t0/t1 toggle bit change when the key 0 or key 1 is press down and release between the two sequence frame. the toggle bit not change for as long as the key remains down. checksum : 3bit check the receive data checksum[2:0] = { address[2:0] } xor { t0, key0[4:3] } xor { key0[2:0] } xor {t1, key1[4:3]} xor { key1[2:0] }; repeat interval: when the key is remain pressed down, the repeat code as below: figure 0-14 14.3 register list irc block address name base address irc 0x0000 table 0-1 irc controller registers offset register name description 0x60 irc _ctl infrared remote control register 0x61 irc_stat infrared remote status register 0x62 irc _cc infrared remote control customer code register 0x63 irc_kdc infrared remote control key free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 155 data code register 0x64 irc_wk infrared remote control wake up key data code register 14.3.1 irc_ctl infrared remote control register default 0x0000 offset = 0x60 bit(s) name description r/w reset 15:4 reserved reserved r 0x0 3 ire irc enable 0: disable 1: enable rw 0x0 2 iie irc irq enable 0: disable 1:enable rw 0x0 1:0 icms irc code mode select 00: 9012 code 01: 8bits nec code 10: rc5 code 11: air code rw 0x0 14.3.2 irc_stat infrared remote control register default 0x0000 offset = 0x61 bit(s) name description r/w reset 15:7 reserved reserved r 0x0 6 ucmp user code don?t match pending bit. write 1 to this bit will clear it, or auto clear if receive the correct user code the next time. 0: user code match 1: user code don?t match rw 0x0 5 kdcm key data code don?t match pending bit. write 1 to this bit will clear it, or auto clear if receive the rw 0x0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 156 correct key data code the next time 0: key data code match 1: key data code don?t match 4 rcd repeated code detected, write 1 to this bit will clear it, otherwise don?t change 0: no repeat code 1: detect repeat code rw 0 3 - reserved r 0x0 2 iip irc irq pending bit, write 1 to this bit will clear it 0: no irq pending 1: irq pending the condition of suspending is that receiving all code correctly. it contains user code and key assignment,received correctly. and if user code and key assignment can received incorrectly, the receiving repeat code which followed this frame cannot happen to suspend. rw 0x0 1 - reserved r 0x0 0 irep irc receive error pending 0: receive ok 1: receive error occurs if not match the protocol. writing 1 to this bit will clear this bit, or auto clear if receive the correct user code and key data code the next time. rw 0x0 14.3.3 irc_cc infrared remote control customer code register default 0x0000 offset = 0x62 bit(s) name description r/w reset 15:0 iccc infrared remote control customer code in rc5 mode: bit 4:0 is the customer code in 9012 and nec mode: bit 15:0 is the customer code, in air mode: rw 0x0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 157 bit2:0 is the address if the received customer code not comply with this register value, error occur. 14.3.4 irc_kdc infrared remote control key data code register default 0x0000 offset = 0x63 bit(s) name description r/w reset 15:0 ikdc irc key data code in rc5 mode: bit 5:0 is the key data in 9012 and nec mode: bit 7:0 is the key data; bit 15:8 is the key anti-data in air mode: bit13 is the toggle bit bit12:8 is the key1 data bit5 is the toggle bit bit 4:0 is the key0 data. if receiving key assignment, register should be update; if receiving repeat code, then register should not update. rw 0x0 14.3.5 irc_wk infrared remote control wake up key data code register default 0x0000 offset = 0x64 bit(s) name description r/w reset 15:0 ikdc irc wake up key data code in rc5 mode: bit 5:0 is the wake up key data in 9012 and nec mode: bit15:0 is the wake up key data; bit 7:0 is the key data; bit 15:8 is the key anti-data in air mode: rw 0x0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 158 bit 4:0 is the wake up key data (use key0 data). if the receiving key assignment is the same as the value of register, then it will generate wakeup signal to pmu mode, and suspending at the same time. free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 159 15. ethernet phy subsystem 15.1features rmii interface support with 50mhz reference clock output to mac smii interface support with 125mhz reference clock output to mac not supports smi interface access the phy regist er directly, the phy register accessed by spi interface single-chip 10base-t and 100bas e-tx physical layer solution fully compliant to 100base-tx /10base-t standards (ieee 802. 3u, fddi-tp-pmd, and ieee 802.3) supports two multi-functional led output supports the full-duplex and half-duplex modes supports auto-mdix for detection and correction with the mdi/mdix auto -crossover function 15.2 function description ? this phy integrated 10/100base-tx (twisted-pair cable) transceiver module achieves the high performance that can be realized in a wide variety of ethernet applications. it is fully compliant with the 10/100base-tx ethernet st andards, such as ieee 802.3, 802.3u, and ansi x3.263-1995 (fddi-tp-pmd). ? this phy offers a choice of rmii or smii data interface connection with the mac processor. the mii serial management bus (smi) of mac ca n not access to this phy?s control and status registers. user can use the spi interface to co nfigure the smi control block of this phy to access the phy?s internal control and status registers. ? this phy does not require a 50mhz and 125mhz system clock. it uses a 24mhz or 25mhz crystal for its input reference clock and outp uts a 50mhz rmii or 125mhz smii reference clock to the mac. ? the transmit and receive function converts th e received/transmitted data based on the ieee 802.3 defined coding standards, such as the parallel-to-serial conversion, 4b/5b,scrambling/de-scrambling, nrz-to-nrzi conversion and mlt3 encoding/decoding. free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 160 16. touch pannel 16.1 features support 4 wire resistance touch panel 12 bit adc resolution,single piont only. x and y direction?s measurement independently sample frequency from 1/4k~32k can be configed as 2-channel adc when touch panel?s function is not required support touch pressure measurement 16.2 function description atc260x integrates an 12 bit sar adc for touch panel or 2-channel adc. when enabled, the adc will work. when ten and tie set, the controller waits for touch and irq occurs while touched. voltage of y2 pulled low will trigger touch. after irq, software should set xyds to enable x or y direction's measurement and adc conversion. otherwise the sar adc would not work. the block will sample the voltage of x1 or y1 and convert the analog voltage to digital bits through sar adc. the adc data is available when ydr/xdr is set. the convert state described as below: figure 2.1-1 the sar adc's frequency (fss) can be set between 1/2k~32k. sampling time duty (std) can be set as 1/8 or 1/16.these parameters are adjustable in demand. the timing described as below: free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 161 figure 2.1-2 sar adc can be enabled by ten or len or ren. when touch panel's function is not required, this module can also be used as a 2-channel adc. touch panel and 2-channel adc must not be used at the same time. len and ren can be set alone or together. touch panel and 2-channel adc share the same control and data register. the data register is common. the bits of control allocated list below. common bits : adcbcs, std, dfen exclusive bits for touch panel: ten, xyds, idle, notch, tie, tip xdr, ydr exclusive bits for 2-channel adc: len, ren, lcie, rcie, lcip, rcip when touch panel's function is selected, the bits distributed to 2-channel adc must not be set, vice versa. the voltage range of tp can be adjusted by setting register. vhlst of tp_ctl0 selects the v-pp of tp. the higher voltage may increase snr of tp, but more power consummation will be taken. touch panel can also be used for waking up system. there are 1 mode function : touch panel can wakeup pmu. x1/x2/y1/y2 share pins with gpio either. 16.3 touch pressure measurement the resistant of touch reflects the touch pressure. so the touch pressure measurement is identified to measure touch r . the bigger of touch r , the less of touch pressure, vice versa. free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 162 16.4 register list ? 16.5 register description ? 17. interrupt controller 17.1 features 16 interrupt sources can be send to intc module of master soc through pin extirq . table 0-1 shows all interrupt sources. details about the interrupt sources can be found in the respective module sections. table 0-2 interrupt sources list interrupt number sources type 0 audio high level 1 tp high level 2 ethernet high level 3 ov high level 4 oc high level 5 ot high level 6 uv high level 7 alarm high level 8 onoff high level 9 wkup high level 10 ir high level 11-15 reserved - note: ov-over voltage, oc-over current, ot-over temperature, uv- under-voltage. if you want to know which interrupt has happened, please refer to register ints_pd, you can mask any of the 16 interrupt sources by setting register ints_msk. free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 163 17.2 block diagram the block diagram is as follows: figure 0-1 17.3 register list interrupt source block base address name base address ints_register 0x200 interrupt source block configuration registers list offset register name description 0x00 ints_pd interrupt pending register 0x01 ints_msk interru pt mask register free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 164 17.4 register description 17.4.1 ints_pd cpu can access the status of interrupt sources by read this register. interrupt pending bit can not be cleared by writing 1,it is not cleared until device pending is cleared. offset = 0x00 bit name description r/w reset 15:11 reserved 10:0 ints_pd[n] interrupt pending bit. interrupt name ?n? accords to interrupt sources table. 0: interrupt source n request is not active 1: interrupt source n request is active. r ints_pd[n] 17.4.2 ints_msk cpu can enable or disable by write this register. 0: interrupt is disabled. 1: interrupt is enabled. offset = 0x01 bits name description r/w reset 15:11 reserved - r/w 0 10 ir ir intterupt mask bit r/w 0 9 wkup wkup interrupt mask bit r/w 0 8 onoff onoff interrupt mask bit r/w 0 7 alarm alarm interrupt mask bit r/w 0 6 uv un-voltage interrupt mask bit r/w 0 5 ot over temperature interrupt mask bit r/w 0 4 oc over current interrupt mask bit r/w 0 3 ov over voltage interrupt mask bit r/w 0 2 ethernet ethernet interrupt mask bit r/w 0 1 tp touch panel interrupt mask bit r/w 0 0 audio audio interrupt mask bit r/w 0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 165 18. general puppose i/o 18.1 features this chapter will describe the multiplexing of the whole system and the gpio function. there are 32 bits general purpose i/o port in atc260x to bring more flexible application possibility. the multiplexing is software controlled and can be configured for different application. 18.2 function description 32 gpios with independent output and input function several different driving capacity of gpios software control fo r multiplexing 18.3 registers list gpio/mfp registers block base address name base address mfp_register 0x300 gpio/mfp registers offset address offset register name description 0x00 mfp_ctl0 multiplexing control 0 0x01 mfp_ctl1 multiplexing control 1 0x10 gpio_outen0 gpio output enable 0 0x11 gpio_outen1 gpio output enable 1 0x12 gpio_inen0 gpio input enable 0 0x13 gpio_inen1 gpio input enable 1 0x14 gpio_dat0 gpio data 0 0x15 gpio_dat1 gpio data 1 0x20 pad_drv0 pad drive capacity0 select 0x21 pad_drv1 pad drive capacity1 select 0x22 pad_en pad enable control free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 166 18.4 register description 18.4.1 mfp_ctl0 multiplexing control register 0 offset=0x00 bits name description r/w default 15: 8 - reserved r 0 7 led1 led1 multiplexing 0: led1 1: gpio29 rw 0 6 led0 led0 multiplexing 0: led0 1: gpio28 rw 0 5 i2s_mclk1_lrclk1_dout i2s_mclk1 i2s_lrclk1 i2s_dout multiplexing 0: i2s_mclk1 i2s_lrclk1 and i2s_dout 1: gpio9 gpio10 and gpio11 rw 0 4 i2s_mclk0_lrclk0 i2s_mclk0 and i2s_lrclk0 multiplexing 0: i2s_mclk0 and i2s_lrclk0 1: gpio6 and gpio7 rw 0 3:2 i2s_din i2s_din multiplexing 00: i2s_din 01: gpio8 10: i2s_dout 11:reserved rw 00 1:0 rmii rmii multiplexing 00: rmii_ref_clk rmii_crs_dv rmii_rxd0 rmii_rxd1 rmii_tx_en rmii_txd0 and rmii_txd1 01: gpio21 ? gpio27 10: smii_clk smii_rx gpio23 ? gpio25 smii_tx and smii_sync 11: reserved rw 00 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 167 18.4.2 mfp_ctl1 multiplexing control register 1 offset=0x01 bits name description r/w defa ult 15:1 4 outswc outswc multiplexing 00: outsw and outc 01: mic1ln and mic1rn 10: gpio4 and gpio5 <800k 11: reserved rw 00 13:1 2 outslr outslr multiplexing 00: outsl and outsr 01: mic1lp and mic1rp 10: gpio2 and gpio3 <800k 11: reserved rw 00 11:10 outsbl r outsblr multiplexing 00: outsbl and outsbr 01: mic0ln and mic0rn 10: gpio0 and gpio1 <800k 11: reserved rw 00 9:8 micinlr micinlr multiplexing 00: micinl and micinr 01: mic0lp and mic0rp 10: dmicclk and dmicdat 11:reserved rw 00 7:5 tp tp multiplexing 111: x1 y1 x2 and y2 000: gpio17 gpio18 gpio19 and gpio20 <1m 010: gpio17 y1 gpio19 and gpio20 <1m 100: x1 gpio18 gpio19 and gpio20 <1m 110: x1 y1 gpio19 and gpio20 <1m others: reserved rw 111 4 remcon remcon multiplexing 0: remcon 1: gpio16 <1m note when this signal be used as gpio16 in a solution, rem_con_wk_en bit in sps_sy s_ctl0 must be cleared before get into standby mode(s2/s3/s4) to avoid waking up rw 0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 168 incorrectly. 3 auxin3 auxin3 multiplexing 0: auxin3 1: gpio15 <1m rw 0 2 auxin2 auxin2 multiplexing 0: auxin2 1: gpio14 <1m rw 0 1 auxin1 auxin1 multiplexing 0: auxin1 1: gpio13 <1m rw 0 0 auxin0 auxin0 multiplexing 0: auxin0 1: gpio12 <1m rw 0 note1: the ( ) follows gpio function is to indicate the maximum speed of the pad in gpio function.more than the speed will affect performance of the adc dac and ethernet mode it ? s suggested that the speed of those pad as slow as possible. note2: when bit 11:8 is set to ?0110?, mic0 l&r must be disabled, other wise dmic pad and mic0 lp&rp pad will conflict each other. when bit 15:12 is set to ?0100?, mic1 l&r must be disabled, other wise outsl&sr pad and mic1lp&rp pad will conflict each other. when bit 15:12 is set to ?0110?, mic1 l&r must be disabled, other wise gpio 2&3 pad and mic1lp&rp pad will conflict each other. be sure that enable mic after mfp is set accurately , and before you change the mfp setting you must make mic disabled 18.4.3 gpio_outen0 gpio output enable register 0 offset=0x10 bits name description r/w reset 15:0 gpio_outen0 gpio[15:0] output enable. 0: disable 1: enable rw 0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 169 18.4.4 gpio_outen1 gpio output enable register 1 offset=0x11 bits name description r/w reset 15:0 gpio_outen1 gpio[31:16] output enable. 0: disable 1: enable rw 0 18.4.5 gpio_inen0 gpio input enable register 0 offset=0x12 bits name description r/w reset 15:0 gpio_inen0 gpio[15:0] input enable. 0: disable 1: enable rw 0 18.4.6 gpio_inen1 gpio input enable register 1 offset=0x13 bits name description r/w reset 15:0 gpio_inen1 gpio[31:16] input enable. 0: disable 1: enable rw 0 18.4.7 gpio_dat0 gpio data register 0 offset=0x14 bits name description r/w reset 15:0 gpio_dat0 gpio[15:0] input/output data. rw 0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 170 18.4.8 gpio_dat1 gpio data register 1 offset=0x15 bits name description r/w reset 15:0 gpio_dat1 gpio[31:16] input/output data. rw 0 18.4.9 pad_drv0 pad driving capacity offset=0x20 bits name description r/w reset 15:5 - reserved r 0 4 spi_miso_drv pad spi_miso drive capacity 0: level 2 (mu1=mu2=0) 1: level 3 (mu1=1,mu2=0) rw 0 3 i2s_din_drv ad i2s_din drive capacity 0: level 3 (mu1=1, mu2=0) 1 :level 4 (mu1=mu2=1) rw 0 2 i2s_dout_drv pad i2s_dout drive capacity 0:level 3 (mu1=1,mu2=0) 1:level 4 (mu1=mu2=1) rw 0 1 dmicclk_drv pad dmicclk drive capacity 0: level 2 (analog mu =0) 1: level 3 (analog mu =1) rw 0 0 extirq_drv pad extirq drive capacity 0: level 2 (mu1=mu2=0) 1: level 3 (mu1=1,mu2=0) rw 0 18.4.10 pad_drv1 pad driving capacity 1 offset=0x21 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 171 bits name description r/w default 15:12 - reserved r 0 11 led0 pad led0 drive capacity 0:level 3 (mu1=1,mu2=0) 1:level 4 (mu1=mu2=1) rw 0 10 led 1 pad led1 drive capacity 0:level 3 (mu1=1,mu2=0) 1:level 4 (mu1=mu2=1) rw 0 9:8 rmii_ref_clk_drv pad rmii_ref_clk drive capacity 00:level 2 (mu1=mu2=0) 01:level 3 (mu1=1,mu2=0) 10:level 4 (mu1=mu2=1) 11: reserved rw 00 7:6 rmii_crs_dv_drv pad rmii_crs_dv drive capacity 00:level 2 (mu1=mu2=0) 01:level 3 (mu1=1,mu2=0) 10:level 4 (mu1=mu2=1) 11: reserved rw 00 5:4 - reserved r 0 3:2 rmii_rxd0_drv pad rmii_rxd0 drive capacity 00:level 2 (mu1=mu2=0) 01:level 3 (mu1=1,mu2=0) 10:level 4 (mu1=mu2=1) 11: reserved rw 00 1:0 rmii_rxd1_drv pad rmii_rxd1 drive capacity 00:level 2 (mu1=mu2=0) 01:level 3 (mu1=1,mu2=0) 10:level 4 (mu1=mu2=1) 11: reserved rw 00 18.4.11 pad_en pad enable control offset=0x22 bits name description r/w default 15:14 reserved r 0 13 pad_en13 1 p_i2s_mclk0 pad enable 0 p_i2s_mclk0 pad disable rw 0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 172 12 pad_en12 1 p_i2s_lrclk0 pad enable 0 p_i2s_lrclk0 pad disable rw 0 11 pad_en11 1 p_i2s_din pad enable 0 p_i2s_din pad disable rw 0 10 pad_en10 1 p_i2s_mclk1 pad enable 0 p_i2s_mclk1 pad disable rw 0 9 pad_en9 1 p_i2s_lrclk1 pad enable 0 p_i2s_lrclk1 pad disable rw 0 8 pad_en8 1 p_i2s_dout pad enable 0 p_i2s_dout pad disable rw 0 7 pad_en7 1 p_rmii_ref_clk pad enable 0 p_rmii_ref_clk pad disable rw 0 6 pad_en6 1 p_rmii_crs_dv pad enable 0 p_rmii_crs_dv pad disable rw 0 5 pad_en5 1 p_rmii_rxd0 pad enable 0 p_rmii_rxd0 pad disable rw 0 4 pad_en4 1 p_rmii_rxd1 pad enable 0 p_rmii_rxd1 pad disable rw 0 3 pad_en3 1 p_rmii_tx_en pad enable 0 p_rmii_tx_en pad disable rw 0 2 pad_en2 1 p_rmii_txd0 pad enable 0 p_rmii_txd0 pad disable rw 0 1 pad_en1 1 p_rmii_txd1 pad enable 0 p_rmii_txd1 pad disable rw 0 0 pad_en0 1 p_extirq pad enable 0 p_extirq pad disable rw 0 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 173 19. pin description 19.1 atc2605 pinassignment free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 174 19.2 ATC2603 pinassignment free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 175 19.3 atc2605/ATC2603 pin definition no. pin name function name i/o description atc2605 ATC2603 1 out1p out1p ao classd1 positive output 1 -- 2 out1n out1n ao classd1 negative output 2 -- 3 cdpvcc1 cdpvcc1 pow er classd1 power 3 -- 4 txop txop ao physical transmit signal (+differential) 4 -- 5 txon txon ao physical transmit signal (-differential) 5 -- 6 agnd_phy agnd_phy ground transmit agnd 6 -- 7 rxip rxip ai physical receive signal (+differential) 7 -- 8 rxin rxin ai physical receive signal (-differential) 8 -- 9 ldo2avcc ldo2avcc power output of voltage regulator ldo2, also for analog io use 9 1 10 ldo2_8in ldo2_8in supply input of voltage regulator ldo2 10 2 11 ldo8out31 ldo8out31 ao output of voltage regulator ldo8 11 -- 12 agnd agnd ground analog power ground 12 3 13 hosci hosci ai connection for 24/25mhz crystal(output from oscilator to cystal) or 24/25mhz external clock input(when not 13 -- free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 176 using crystal) 14 hosco hosco ao connection for 24/25mhz crystal(input to oscilator from cystal) 14 4 15 ldosvcc ldosvcc power output of voltage regulator ldo11, the io power for standby mode 15 5 16 lowp lowp do ddr s2 isolation signal 16 -- 17 wkup wkup di external wakeup signal input 17 -- 18 ir ir di ir reciver signal 18 6 19 por por do power on reset output to main controller 19 7 20 onoff onoff di onoff key input/reset signal 20 8 21 losco losco aio crystal oscillator input of 32.768khz 21 9 22 losci losci ai crystal oscillator output of 32.768khz 22 10 23 ldortcvd d ldortcvdd power output of voltage regulator ldo12 23 11 24 wallfet_ en wallfet_en ao gate signal of external mosfet connected to wall 24 12 25 batfet_en batfet_en ao gate signal of external mosfet connected to bat 25 13 26 wall wall supply connected to wall adapter power 26 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 177 supply 27 wall wall supply connected to wall adapter power supply 27 14 28 wall wall supply connected to wall adapter power supply 28 -- 29 vbus vbus supply connected to usb power supply 29 15 30 syspwr syspwr power system power 30 16 31 syspwr syspwr power system power 31 17 32 syspwr syspwr power system power 32 33 bat bat supply connected to battery power supply 33 18 34 bat bat supply connected to battery power supply 34 19 35 bat bat supply connected to battery power supply 35 -- 36 bkbat bkbat supply bakeup battrey power supply 36 -- 37 vdd vdd power core logic power 37 20 38 ldo7out18 ldo7out18 ao output of voltage regulator ldo7 38 21 39 auxin0 auxin0 aio gerenal adc input0 39 22 40 auxin1 auxin1 aio gerenal adc input1 40 23 41 auxin2 auxin2 aio gerenal adc input2 41 -- 42 auxin3 auxin3 aio gerenal adc input3 42 -- 43 remcon remcon aio gerenal adc input4, for remote control 43 24 44 ldo9out12 ldo9out12 ao output of voltage regulator ldo9 44 25 45 ldo6out10 ldo6out10 ao output of voltage regulator ldo6 45 26 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 178 46 ldo5out28 ldo5out28 ao output of voltage regulator ldo5 46 27 47 ldo5in ldo5in supply input of voltage regulator ldo5 47 28 48 dc4drv dc4drv ao dc-dc4 drive pin 48 -- 49 dc4out50 dc4out50 ao dc-dc4 49 -- 50 dc5drv dc5drv ao dc-dc5 drive pin 50 -- 51 dc5fbled dc5fbled ai dc-dc5 feedback pin 51 -- 52 iled iled ai 52 -- 53 dc2lx dc2lx ao dc-dc2 inductor connection 53 -- 54 dc2lx dc2lx ao dc-dc2 inductor connection 54 -- 55 dc2lx dc2lx ao dc-dc2 inductor connection 55 29 56 dc2vin dc2vin supply dc-dc2 power input 56 30 57 dc2vin dc2vin supply dc-dc2 power input 57 -- 58 dc2voutv ddr dc2voutvddr ao output of dc-dc2 58 31 59 dc3vout31 dc3vout31 power output of dc-dc3 59 32 60 dc3vin dc3vin supply dc-dc3 power input 60 33 61 dc3vin dc3vin supply dc-dc3 power input 61 34 62 dc3vin dc3vin supply dc-dc3 power input 62 -- 63 dc3lx dc3lx ao dc-dc3 inductor connection 63 35 64 dc3lx dc3lx ao dc-dc3 inductor connection 64 36 65 dc3lx dc3lx ao dc-dc4 inductor connection 65 -- 66 ldo4out33 ldo4out33 ao output of voltage regulator ldo4 66 -- free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 179 67 ldo4in ldo4in supply input of voltage regulator ldo4 67 -- 68 switch1o ut switch1out power output of voltage regulator switch1 68 37 69 switch1in switch1in supply input of voltage regulator switch1 69 38 70 dc1lx dc1lx ao dc-dc1 inductor connection 70 39 71 dc1lx dc1lx ao dc-dc1 inductor connection 71 -- 72 dc1lx dc1lx ao dc-dc1 inductor connection 72 40 73 dc1vin dc1vin supply dc-dc1 power input 73 41 74 dc1vin dc1vin supply dc-dc1 power input 74 42 75 dc1vin dc1vin supply dc-dc1 power input 75 -- 76 dc1vout10 dc1vout10 power output of dc-dc1 76 43 77 sw2out sw2out power output of voltage regulator switch2 77 -- 78 sw2in sw2in supply input of voltage regulator switch2 78 -- 79 ldo1out ldo1out ao output of voltage regulator ldo1 79 44 80 ldo1_10in ldo1_10in supply input of voltage regulator ldo1&ldo10 80 45 81 ldo10out2 5 ldo10out25 ao output of voltage regulator ldo10 81 -- y2 touch panel y2 82 y2 gpio20 aio general purpose input/output 20 82 -- y1 touch panel y1 83 y1 gpio18 aio general purpose input/output 18 83 -- x1 touch panel x1 84 x1 gpio17 aio general purpose input/output 17 84 -- free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 180 x2 touch panel x2 85 x2 gpio19 aio general purpose input/output 19 85 -- 86 vdd vdd power core logic power 86 46 87 spi_ss spi_ss di spi slave select 87 47 88 spi_clk spi_clk di spi slave clock 88 48 89 spi_mosi spi_mosi di spi slave input 89 49 90 spi_miso spi_miso do spi slave output 90 50 i2s_mclk1 i2s master clock1 91 i2s_mclk1 gpio9 dio general purpose input/output 9 91 -- i2s_lrclk1 i2s lr clock1 92 i2s_lrclk1 gpio10 dio general purpose input/output 10 92 -- i2s_dout i2s data output 93 i2s_dout gpio11 dio general purpose input/output 11 93 51 i2s_din i2s data input i2s_dout i2s data output 94 i2s_din gpio8 dio general purpose input/output 8 94 52 i2s_lrclk0 i2s lr clock0 95 i2s_lrclk0 gpio7 dio general purpose input/output 7 95 53 i2s_mclk0 i2s master clokck0 96 i2s_mclk0 gpo6 dio general purpose input/output 6 96 54 97 extirq extirq do irq outpur signal 97 55 98 led0 led0 dio link led/traffic led 98 -- 99 led1 led1 dio link speed led 99 -- free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 181 rmii_refclk rmii synchronous 50mhz clock reference for receive, transmit and control interface. smii_clk smii synchronous 125mhz clock reference for receive, transmit and control interface. 100 rmii_refc lk gpio21 dio general purpose input/output 21 100 -- rmii_rxd0 rmii receive data0; 101 rmii_rxd0 gpio23 dio general purpose input/output 23 101 -- rmii_rxd1 rmii receive data1 102 rmii_rxd1 gpio24 dio general purpose input/output 24 102 -- rmii_crsdv rmii carrier sense/receive data valid smii_rx smii receive data 103 rmii_crsd v gpio22 dio general purpose input/output 22 103 -- rmii_txen rmii transmit enable 104 rmii_txen gpio25 dio general purpose input/output 25 104 -- rmii_txd0 rmii transmit data0; smii_tx smii transmit data 105 rmii_txd0 gpio26 dio general purpose input/output 26 105 -- rmii_txd1 rmii transmit data1; 106 rmii_txd1 smii_sync dio smii synchronization 106 -- free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 182 gpio27 general purpose input/output 27 107 vcc vcc power digital io power 107 56 108 vmicext vmicext ao external mic bias 108 57 109 vmicin vmicin ao internal mic bias 109 -- micinr micr channel input mic0rp mic0r positive channel input when use as differential 110 micinr dmicdat ai data signal of digital mic 110 58 outsbr back surround right channel output mic0rn mic0r negetive channel input when use as differential 111 outsbr gpio1 aio general purpose input/output 1 111 -- micinl micl channel input mic0lp mic0l positive channel input when use as differential 112 micinl dmicclk ai clock signal of digital mic 112 -- outsbl back surround left channel output 113 outsbl mic0ln aio mic0l negetive channel input when use as 113 -- free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 183 differential gpio0 general purpose input/output 0 114 vro vro ao vr output 114 59 115 vrefi vrefi aio reference voltage,with capacitance 115 60 116 vros vros ao vro sense 116 61 117 fminr fminr ai fmr channel input 117 62 118 fminl fminl ai fml channel input 118 63 outsr surround right channel output mic1rp mic1r positive channel input when use as differential 119 outsr gpio3 aio general purpose input/output 3 119 -- outc center channel output mic1rn mic1r negetive channel input when use as differential 120 outc gpio5 aio general purpose input/output 5 120 -- outsl surround left channel output 121 outsl mic1lp aio mic1l positive channel input when use as differential 121 -- free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 184 gpio2 general purpose input/output 2 outsw subwoofer channel output mic1ln mic1l negetive channel input when use as differential 122 outsw gpio4 aio general purpose input/output 4 122 -- 123 outfl outfl ao front left channel output 123 64 124 pagnd pagnd ground ground of pa power 124 -- 125 outfr outfr ao front right channel output 125 65 126 cdpvcc2 cdpvcc2 pow er classd2 power 126 66 127 out2n out2n ao classd2 negative output 127 67 128 out2p out2p ao classd2 positive output 128 68 free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 185 20 package and ordering information 20.1 package drawing atc2605 package drawing free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 186 ATC2603 package drawing free datasheet http:///
atc260x datasheet copyright ? actions semiconductor co., ltd. 2012. all rights reserved. version 1.1 page 187 actions semiconductor co., ltd. address: ?o? 1 , tangjia, zhuhai, guangdong, china tel: +86-756-3392353 fax: +86-756-3392251 post code: 519085 http://www.actions-semi.com business email: mp-sales@actions-semi.com technical service email: mp-cs@actions-semi.com free datasheet http:///

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